A 256m Dram With Simplified Register Control For Low Power Self Refresh And Rapid Burn-in

Yoo, Seung-Moon; Han, Jin Man; Haq, Ejaz Ul; Yoon, Sei Seung; Jeong, Se-Jin; Kim, Byung Chul; Lee, Jung-Hwa; Jang, Tae-Seong; Kim, Hyung-Dong; Park, Chan Jong; Seo, Dong Il; Choi, Chun Sik; Cho, Soo-In; Hwang, C.G.

doi:10.1109/vlsic.1994.586228

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A 256m Dram With Simplified Register Control For Low Power Self Refresh And Rapid Burn-in

Cited by 6 publications

References 2 publications

A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme

A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme

A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor

New improved low power and high SNM single metal SRAM in 32 nm technology

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