A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme

Tsukude, M.; Kuge, S.; Fujino, Tadashi; Arimoto, Kazutami

doi:10.1109/4.641692

Cited by 8 publications

(2 citation statements)

References 13 publications

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“…To improve the sensing performance in low voltage, charge-transferred presensing (CTPS) scheme [1] has been proposed. The circuit and timing waveform of the conventional CTPS are shown in Fig.…”

Section: Charge-transferred Presensing (Ctps) and Conventional Sementioning

confidence: 99%

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A Sense Amplifier Scheme with Offset Cancellation for Giga-bit DRAM

Kang¹,

Hong²,

Chang³

et al. 2007

JSTS:Journal of Semiconductor Technology and Science

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To improve low sense margin at low voltage, we propose a negatively driven sensing (NDS) scheme and to solve the problem of WL-to-BL short leakage fail, a variable bitline reference scheme with freelevel precharged bitline (FLPB) scheme is adopted. The influence of the threshold voltage offset of NMOS and PMOS transistors in a latch type sense amplifier is very important factor these days. From evaluating the sense amplifier offset voltage distribution of NMOS and PMOS, it is well known that PMOS has larger distribution in threshold voltage variation than that of NMOS. The negativelydriven sensing (NDS) scheme enhances the NMOS amplifying ability. The offset voltage distribution is overcome by NMOS activation with NDS scheme first and PMOS activation followed by time delay. The sense amplifier takes a negative voltage during the sensing and amplifying period. The negative voltage of NDS scheme is about-0.3V to-0.6V. The performance of the NDS scheme for DRAM at the gigabit level has been verified through its realization on 1-Gb DDR2 DRAM chip. Index Terms-DRAM, charge-transferred presensing (CTPS), negatively-driven sensing(NDS), free-level precharged bitline(FLPB), sense amplifier offset voltage, threshold voltage distribution.

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Section: Charge-transferred Presensing (Ctps) and Conventional Sementioning

confidence: 99%

“…Memory circuits, such as dynamic random access memory (DRAM) arrays, have increased in complexity and density over time. To meet the technology trend, the memory circuits should adopt the low voltage and low power based scheme [1] [2].…”

Section: Introductionmentioning

confidence: 99%