A 256-Mb SDRAM using a register-controlled digital DLL

Hatakeyama, A.; Mochizuki, H.; Aikawa, T.; Takita, M.; Ishii, Yoshikazu; Tsuboi, Hideyuki; Fujioka, Shogo; Yamaguchi, S.; Koga, M.; Serizawa, Y.; Nishimura, Koki; Kawabata, K.; Okajima,; Kawano, Michiari; Kojima, Hisashi; Mizutani, Kana; Anezaki, T.; Hasegawa, Michiko; Taguchi, M.

doi:10.1109/4.641693

Cited by 51 publications

(12 citation statements)

References 2 publications

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“…A time-to-digital converter (TDC) was proposed to prevent the harmonic locking problem but it has significant area overhead [20]. Yet another problem is that large areas are also required by the shift register in [21]- [23] and the binary-to-thermometer converter (BTC) in [24], which are used to control an equally weighted digital delay line.…”

Section: Introductionmentioning

confidence: 99%

Process Variation Tolerant All-Digital 90$^{\circ}$ Phase Shift DLL for DDR3 Interface

Kang

Ryu

Jung

et al. 2012

IEEE Trans. Circuits Syst. I

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An all-digital 90 phase shift delay lock loop (DLL) is presented, which is robust against the delay mismatch caused by process variation. Each of the four 90 phase shift blocks accurately aligns its output to a 90 shifted phase using its own ring oscillator and locking delay code. It is analytically proved that the phase shift accuracy of the proposed 90 phase shift block is always higher than that of the conventional all-digital 90 phase shift DLL. The harmonic locking problem is prevented by a ring oscillator and a counter. An area-efficient binary-to-thermometer converter is proposed to reduce the area overhead caused by the delay-line control logic. A fast operating frequency with a finer resolution is achieved through the fine delay range selector and the resistance controlled fine delay unit. The proposed 90 phase shift DLL is implemented using a 45-nm CMOS process. The phase shift accuracy errors at the 90 and 270 phases are 0.43 and 1.01 , respectively, when the maximum locking delay code difference between the four 90 phase shift delay lines corresponds to at 800 MHz. It proves that the DLL corrects the significant phase error caused by process variation. The power consumption is 3.3 mW at 800 MHz.Index Terms-BTC, delay mismatch, digital DLL, multiphase, process variation, 90 phase shift.

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Section: Introductionmentioning

confidence: 99%

Process Variation Tolerant All-Digital 90$^{\circ}$ Phase Shift DLL for DDR3 Interface

Kang

Ryu

Jung

et al. 2012

IEEE Trans. Circuits Syst. I

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“…Changing the effective resistance or capacitance adjusts the element delay [3,4]. These kinds of delay line elements are very efficient in DLLs where small, accurate and precise amount of delay is required, and may be used to fine-grain delay variation.…”

Section: Introductionmentioning

confidence: 99%

Current controlled delay line elements' improvement study

Kolodziejski

Kuta

Jasielski

2012

2012 International Conference on Signals and Electronic Systems (ICSES)

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The chain of delay elements creating delay lines are the basic building blocks of delay locked loops (DLLs) applied in clock distribution network in many VLSI circuits and systems. In the paper Current Controlled delay line (CCDL) elements with Duty Cycle Correction (DCC) has been described and investigated. The architecture of these elements is based on Switched-Current Mirror Inverter (SCMI) and CMOS standard or Schmitt type inverters. The primary characteristics of the described CCDL element have been compared with characteristics of two most popular ones: current starved, and shunt capacitor delay elements. The simulation results with real foundry parameters models in 180 nm, 1.8 V CMOS technology from UMC are also included. Simulations have been done using BSIM3V3 device models for Spectre from Cadence Design Systems.

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“…The register-controlled digital DLL is proposed in [13] to provide an all-digital solution for the DLL design. For multiphase clock generation applications, this DLL can overcome the false-lock problem by setting the delay line in minimum delay time at the beginning of phase acquisition.…”

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confidence: 99%

A New DLL-Based Approach for All-Digital Multiphase Clock Generation

Chung

Lee

2004

IEEE J. Solid-State Circuits

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Abstract-A new DLL-based approach for all-digital multiphase clock generation is presented. By using the time-to-digital converter (TDC) with fixed-step search scheme, the proposed all-digital and cell-based solution can overcome the false-lock problem in conventional designs. Furthermore, the proposed all-digital multiphase clock generator (ADMCG) can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity in many different applications. The test chip shows that our proposal demonstrates a wide frequency range to meet the needs of many digital communication applications.Index Terms-Delay-locked loops (DLLs), digitally controlled delay line (DCDL), multiphase clock generation, phase synchronization.

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A 256-Mb SDRAM using a register-controlled digital DLL

Cited by 51 publications

References 2 publications

Process Variation Tolerant All-Digital 90$^{\circ}$ Phase Shift DLL for DDR3 Interface

Process Variation Tolerant All-Digital 90$^{\circ}$ Phase Shift DLL for DDR3 Interface

Current controlled delay line elements' improvement study

A New DLL-Based Approach for All-Digital Multiphase Clock Generation

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