A 250 MHz 5 W RISC microprocessor with on-chip L2 cache controller

Reed, Paul; Alexander, M.; Álvarez, José Marcos Alonso; Brauer, M.; Chao, Chai-Chin; Croxton, C.; Eisen, L.; Le, Toan; Ngo, Tai; Nicoletta, C.; Sanchez, H.; Taylor, Scott A.; Vanderschaaf, N.; Gerosa, G.

doi:10.1109/isscc.1997.585463

Cited by 7 publications

(2 citation statements)

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“…The present paper relaxes this rule by allowing the feed-forward connections between the Prelogic and Postlogic as shown in Figure 1. Feed-forward connections may be found in modern microprocessor chips [1,6,7,10, 21] for improving performance. With this feature, when the array is written with certain data, the same data is also available in the "same cycle" at the array output to a potential read operation intending to read this new data, thus saving one cycle.…”

Section: Introductionmentioning

confidence: 99%

BIST Analysis of an Embedded Memory Associated Logic

Savir

2000

VLSI Design

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Of late some interesting and useful work has been done on the problem of testing logic surrounding embedded memories. This work assumes that the logic surrounding the memory is functionally partitioned and that the different partitions are logically isolated one from the other.This paper expands upon past work using a more flexible design rule which allows feed-forward connections between the data-path Prelogic and Postlogic. The connections are such that there is no feedback from the memory outputs to its inputs, and both the Prelogic and the Postlogic are disconnected from the Address and Control logic. Under this design rule we show the auxiliary circuits used to determine the random pattern testability of faults in the circuitry driving the address inputs and the controls of the two-port memory.The techniques described herein are intended to be used in conjunction with the cutting algorithm for testability measurement in built-in self-test (BIST) designs [2, 11, 17], but may also be suitable for use with other detection probability tools [9, 19], and simulation tools [20].

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Section: Introductionmentioning

confidence: 99%

BIST Analysis of an Embedded Memory Associated Logic

Savir

2000

VLSI Design

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“…Traditionally, the bitline swings during a read access have been limited by using active loads of either diode-connected nMOS or resistive pMOS [10], [11], but these clamp the bitline swing at the expense of a steady bitline current. A more powerefficient way of limiting the bitline swings is to use high-impedance bitline loads and pulse the wordlines [12]- [15]. Bitline power can be further minimized by controlling the wordline pulsewidth to be just wide enough to guarantee the minimum bitline swing development.…”

Section: Introductionmentioning

confidence: 99%

A replica technique for wordline and sense control in low-power SRAM's

Amrutur¹,

Horowitz²

1998

IEEE J. Solid-State Circuits

166

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With the migration toward low supply voltages in low-power SRAM designs, threshold and supply voltage fluctuations will begin to have larger impacts on the speed and power specifications of SRAM's. We present techniques based on replica circuits which minimize the effect of operating conditions' variability on the speed and power. Replica memory cells and bitlines are used to create a reference signal whose delay tracks that of the bitlines. This signal is used to generate the sense clock with minimal slack time and control wordline pulsewidths to limit bitline swings. We implemented the circuits for two variants of the technique, one using bitline capacitance ratioing in a 1.2-m 8-kbyte SRAM, and the other using cell current ratioing in a 0.35m 2-kbyte SRAM. Both the RAM's were measured to operate over a wide range of supply voltages, with the latter dissipating 3.6 mW at 150 MHz at 1 V and 5.2 W at 980 kHz at 0.4 V.

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