A 24 GHz Class-A power amplifier in 0.13um CMOS technology

Khan, Hashim Raza; Wahab, Q.

doi:10.1109/iccrd.2011.5764203

Cited by 3 publications

(1 citation statement)

References 7 publications

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“…This helps in delivering faster and superior RF (radio frequency) performances. Several power amplifier designs are reported without a linearizer, examples include cascode [1][2][3][4][5], three stage common source [6], two stage current mirror [7], and triple stacked single stage transistors [8]. These designs allow for bigger bandwidth, higher gain, and better power handling capabilities.…”

Section: Introductionmentioning

confidence: 99%

The Design and Process Reliability Analysis of Millimeter Wave CMOS Power Amplifier with a Cold Mode MOSFET Linearization

Quadir,

Jain,

Kashfi

et al. 2023

IET Circuits, Devices & Systems

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A power amplifier design operating at 28 GHz for communication applications is presented in this paper. Analog predistorted technique is used to improve the linearity using a cold mode MOSFET linearizer. The paper reports +19.8 dBm of peak power at the output and power-added efficiency (PAE) of 17% is attained by the designed circuit. The 1-dB compression point linearity was +18.6 dBm. The adjacent channel power ratio (ACPR) simulations were performed for the different communication standards like 802_11n_40M, CDMA, IS-95, and 802_11n_20M. Design specification variations of the amplifier have been analyzed over five process corners and simulations were performed to validate compliance with standards and robustness of the designed circuit. Monte Carlo simulation were performed to assess the performance over statistical variability of PAE and power gain. It is believed that this linearization design and the verifications used are done for the first time on a 65-nm RFCMOS process.

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