A 24-bit multi-functional sensor analog front end employing low noise biasing technique with 8.2nV/√Hz input referred noise

Maruyama, Masahiko; Taguchi, Shigenari; Yamanoue, Masafumi; Iizuka, Kunihiko

doi:10.1109/asscc.2015.7387485

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2018

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“…The NMOS input devices are adopted to maximize the g m =I D efficiency. Both input devices are designed to operate in a subthreshold region to enhance the noise performance [13]. The prototype delta-sigma modulator was fabricated in a 0.18 µm CMOS process.…”

Section: Circuit Implementationsmentioning

confidence: 99%

A 101 dB dynamic range, 2 kHz bandwidth delta-sigma modulator with a modified feed-forward architecture

Cho

Kwak

Kim

et al. 2018

IEICE Electron. Express

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This paper presents a modified feed-forward (FF) delta-sigma modulator architecture that simplifies the switched-capacitor network of an analog adder in front of the quantizer. By eliminating the internal FF path from the first integrator output, the number of capacitors in the analog adder is reduced and the load capacitance of the first integrator becomes independent of the quantizer resolution. To verify the proposed modulator architecture, a three-bit second-order delta-sigma analog-to-digital converter (ADC) is implemented. The prototype ADC is fabricated in a 0.18 µm CMOS process with an active die area of 0.095 mm 2. It achieves a dynamic range (DR) of 101.0 dB and a peak signal-to-noise and distortion ratio (SNDR) of 97.1 dB in a 2 kHz signal bandwidth while consuming 63.4 µW from a 1.8 V/1.65 V power supply.

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Section: Circuit Implementationsmentioning

confidence: 99%