1987
DOI: 10.1109/jssc.1987.1052803
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A 21-ns 32 K×8 CMOS static RAM with a selectively pumped p-well array

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Cited by 14 publications
(1 citation statement)
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“…Within the first group, in [52] resistances in series with the NMOS and PMOS supply terminals in the last stage of the driver are used to reduce rising and falling times, negatively affecting the delay. In [53] the resistances are serially added to the gate transistor outputs and their value is controlled with an external voltage so that an optimum value of the control voltage can be found for each load capacity that eliminates ringing in the outputs due to switching.…”
Section: Low Noise Output Driver Design Techniquesmentioning
confidence: 99%
“…Within the first group, in [52] resistances in series with the NMOS and PMOS supply terminals in the last stage of the driver are used to reduce rising and falling times, negatively affecting the delay. In [53] the resistances are serially added to the gate transistor outputs and their value is controlled with an external voltage so that an optimum value of the control voltage can be found for each load capacity that eliminates ringing in the outputs due to switching.…”
Section: Low Noise Output Driver Design Techniquesmentioning
confidence: 99%