A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth

Choi, Yong‐Sang; Song, Ickhyun; Park, Mu-Hui; Chung, Hoeju; Chang, Sanghoan; Cho, Beakhyoung; Kim, Jin‐Young; Oh, Younghoon; Kwon, Duckmin; Jung, Sunghwan; Shin, Jun-Ho; Rho, Yoohwan; Lee, Changsoo; Kang, Min Gu; Lee, Jaeyun; Kwon, Yonghoon; Kim, Soehee; Kim, Jaehwan; Lee, Yong-Jun; Wang, Qi; Cha, Sooho; Ahn, Su−Jin; Hasegawa, Hideki; Lee, Jae‐Wook; Kim, Ki-Sung; Joo, Hyonam; Lee, Kwang-Jin; Lee, Yeong-Taek; Yoo, Jung-Keun; Jeong, Gitae

doi:10.1109/isscc.2012.6176872

Cited by 228 publications

(119 citation statements)

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“…In our experiment, we prototype AG-ckpt with the characteristics of PCM which is the most closest to commercial deployment [29]. As PCM is not available on the market, we use DRAM to save the checkpoint file.…”

Section: Experiments Setupmentioning

confidence: 99%

Understanding the Impact of BPRAM on Incremental Checkpoint

Lü

Wang

et al. 2013

IEICE Trans. Inf. & Syst.

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SUMMARYExisting large-scale systems suffer from various hardware/software failures, motivating the research of fault-tolerance techniques. Checkpoint-restart techniques are widely applied fault-tolerance approaches, especially in scientific computing systems. However, the overhead of checkpoint largely influences the overall system performance. Recently, the emerging byte-addressable, persistent memory technologies, such as phase change memory (PCM), make it possible to implement checkpointing in arbitrary data granularity. However, the impact of data granularity on the checkpointing cost has not been fully addressed. In this paper, we investigate how data granularity influences the performance of a checkpoint system. Further, we design and implement a high-performance checkpoint system named AG-ckpt. AG-ckpt is a hybrid-granularity incremental checkpointing scheme through: (1) lowcost modified-memory detection and (2) fine-grained memory duplication. Moreover, we also formulize the performance-granularity relationship of checkpointing systems through a mathematical model, and further obtain the optimum solutions. We conduct the experiments through several typical benchmarks to verify the performance gain of our design. Compared to conventional incremental checkpoint, our results show that AG-ckpt can reduce checkpoint data amount up to 50% and provide a speedup of 1.2x-1.3x on checkpoint efficiency.

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Section: Experiments Setupmentioning

confidence: 99%

Understanding the Impact of BPRAM on Incremental Checkpoint

Lü

Wang

et al. 2013

IEICE Trans. Inf. & Syst.

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“…This inadvertent bit flip during the write process is referred to as a Write Disturbance. This phenomenon has been reported in by Lee et al [52] in 54 nm technology, and has become a dominant issue below 20nm [20]. For reliable operation, write disturbance issues in PCM need to be reduced or eliminated.…”

Section: Introductionmentioning

confidence: 73%

“…For instance, in a 20 nm PCM prototype [20], they proposed leaving 20 nm of extra space to provide a thermal band along word-lines to prevent a write disturbance. This approach eliminates write disturbance, at the cost of reducing chip capacity.…”

Section: Prior Work: Write Disturbancementioning

confidence: 99%

“…Second, the limits on current delivery of the charge pumps in the PCM peripheral determines the number of parallel cell writes. For example, in a 20 nm PCM prototype, 128 cells can be written in parallel [20]. As we increase the number of written cells, we increase the number of required write slots to update the entire data block (i.e., 512 bits).…”

Section: Prior Work: Write Disturbancementioning

confidence: 99%

“…PCM has a number of desirable characteristics, including zero leakage power and the ability to retain cell state for more than ten years [36]. These features pave the way for PCM to be mass produced and commercialized [6,21]. Compared to DRAM, PCM has better scalability, comparable read latency, but lower per-cell endurance.…”

Section: Introductionmentioning

confidence: 99%

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Ever since the emergence of the electrical computer and the Von Neumann model, computer architects have adhered to a well‐structured hierarchy of memory solutions, clearly trading off performance and capacity with cost. The ubiquitous memory technologies, dominated by SRAM, DRAM, Flash, and magnetic hard disks, are each situated in a well‐defined location within this hierarchy. However, as processes have scaled into deep nanometer feature sizes and the demand for larger capacities and bandwidths increases, these traditional options face tough challenges and may be limited in their ability to continue to provide the new requirements. New technologies, such as phase change memory (PCM), magnetic RAM (MRAM), and resistive RAM (RRAM), have been researched and developed over the recent past in an attempt to meet these demands and replace some or all of the traditional technologies. In this article, the primary technologies are overviewed, including those that currently fill the memory hierarchy pyramid, the primary candidates to join or replace them in the near‐term, and a number of newer candidates that may arise as legitimate solutions in the farther term. In addition, an overview of the current state of processing within the emerging memory technologies is provided, as an attempt to break free of the traditional Von Neumann paradigm to overcome the energy and performance bottlenecks in modern systems.

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A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth

Cited by 228 publications

References 3 publications

Understanding the Impact of BPRAM on Incremental Checkpoint

Understanding the Impact of BPRAM on Incremental Checkpoint

Architectural support for designing dependable non-volatile main memories

Emerging Memory Structures for VLSI Circuits

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