A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B.

Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies

“…The above techniques are discussed from the angle of the phase relationship adjustment. According to the synchronization relationship between clocks used to sample data locally and clocks used to generate data at transmitters, the clocking strategies can also be classified into (1) system or global clocking [4,6,11], where the reference clock is shared by both sides; (2) source synchronous/forwarded clocking [3,9,10,12,13], where a clock is fed from transmitters along data channels; (3) embedded clocking [7,8,22], where a clock is embedded into data at the transmitter, and then is extracted at the receiver; (4) local clocking [20,21,[24][25][26][27][28][29][30][31][32][33][34], where clocks are synthesized locally. (1) ~ (3) belong to synchronous, or mesochronous clocking strategies, which is applicable to applications A ~ C, and almost all of conventional CDR (clock and data recovery) techniques can be used; whereas (4) belongs to plesiochronous one, which is preferable to application C, and PI/PS (phase interpolation/ phase selection) type and blind-oversampling (blindoversampling) techniques are usually used [2,35].…”

A Highly Expandable Forwarded-Clock Receiver with Ultra-Slim Data Lane using Skew Calibration by Multi-Phase Edge Monitoring

“…In addition, the weightadjusted dual-interpolating delay cell, which is used in the multiphase DLL, guarantees sufficient phase linearity without using dummy delay cells, while offering a high-frequency operation. The proposed receiver is designed in the 90-nm CMOS technology, and achieves error-free eye openings of more than 0.5 UI across 9-28 inch Nelco4000-6 microstrips at [4][5][6][7] Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only 0.152 mm 2 and consumes 69.8 mW, while the rest of the receiver occupies 0.297 mm 2 and consumes 56.0 mW at the 7-Gb/s data-rate and supply voltage of 1.35 V.…”

“…A simple architecture in each lane of data transmission is desired while an accurate clock recovery on the receiver is required for a low bit error rate. To meet these demands, many candidates for the transceiver architectures of serial-data communication have been reported in the literature, including source-synchronous clocking architectures such as forwarded-clock transceivers [7] and embedded-clock transceivers [8]. A source-synchronous clocking architecture is a simple solution to increase aggregate I/O bandwidth, while reducing channel complexity.…”

Power Efficiency Comparisons of Interchip Optical Interconnect Architectures

“…The decision circuit is assumed to have 20 mV pp input threshold ambiguity and 30 fF input capacitance, consistent with typical high-speed electrical deserializing decision circuit blocks [16].…”