Both power efficiency and per-channel data rates of high-speed input/output (I/O) links must be improved in order to support future inter-chip bandwidth demand. In order to scale data rates over band-limited channels, various types of equalization circuitry are used to compensate for frequency-dependent loss. However, this additional complexity introduces power and area costs, requiring selection of an appropriate I/O equalization architecture in order to comply with system power budgets. This paper presents a design flow for power optimization of highspeed electrical links at a given data rate, channel type, and process technology node, which couples statistical link analysis techniques with circuit power estimates based on normalized transistor parameters extracted with a constant current density methodology. The design framework selects the optimum equalization architecture, circuit logic style (CMOS versus currentmode logic), and transmit output swing for minimum I/O power. Analysis shows that low loss channel characteristics and minimal circuit complexity, together with scaling of transmitter output swing allows excellent power efficiency at high data rates.Index Terms-Decision-feedback equalization, electrical interconnects, feed-forward equalization, high-speed I/O link, power minimization, serial transceiver.
An I/O design framework is presented which combines statistical link analysis with circuit power models to predict the power-optimum equalization architecture, circuit style, and transmit swing at a given data rate, channel, and process node.
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