A 200mV 32b subthreshold processor with adaptive supply voltage control

Luetkemeier, Sven; Jungeblut, Thorsten; Porrmann, Mario; Rueckert, Ulrich

doi:10.1109/isscc.2012.6177101

Cited by 21 publications

(20 citation statements)

References 5 publications

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“…2. First, thanks to positive synchronous reference frame transformation, load current in synchronous reference frame can be derived as equation (2). It can be concluded all the (6k AE 1)th ðk ¼ 1; 2; 3 .…”

Section: Proposed Harmonic Dectetion Methodsmentioning

confidence: 99%

“…Extracting the Harmonics which need to be compensated as reference current determine the steady state compensation accuracy and dynamic response capability of the active power filter. The traditional method based on the instantaneous reactive power theory [2,3,4,5,6], when the load steps dynamically, the DClink voltage may jump greatly. The SDFT method based on the abc coordinate system has been widely used in harmonic refrence current calculation [6,7,8,9], but it has an inherent latency of 1 fundamental grid cycle [10,11], which makes the system dynamic performance becomes poor, reducing the compensation accuracy.…”

Section: Introductionmentioning

confidence: 99%

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An optimized reference current detection method for active power filter

Chen

2017

IEICE Electron. Express

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An optimized reference current detection method based on synchronous reference frame transformation and sliding discrete Fourier transform (SDFT) is proposed. The proposed method can be used to extract characteristic harmonic currents as the reference current of system from the load currents by fewer sampling points, meanwhile, the numbers of harmonics need to be calculated will reduce to half of traditional method, it means that the proposed method can reduce the computational effort and easy to engineering implementation, while achieving better dynamic performance compared with other methods. The results of simulation and experiment show the validity of this method.

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Section: Proposed Harmonic Dectetion Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An optimized reference current detection method for active power filter

Chen

2017

IEICE Electron. Express

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“…The essential elements considered in WL algorithm are erase count number (ECN) [2], using density [3] and garbage collection (GC) efficiency [4]. However, the effect of WL algorithms highly depends on the application environment [5]. Owing to the scaling of Flash technology, the variance across blocks or among the Flash pages within a block becomes increasingly significant.…”

Section: Recent Researches On Ssd's Reliability Optimizationmentioning

confidence: 99%

“…Also, the pages in a block deteriorate in different speeds. Jimenez et al in [7] suggested a wear unleveling (WU) method to alleviate the pressure in weak pages. However, the RBERs of Flash pages are determined by many factors and changing over time.…”

Section: Recent Researches On Ssd's Reliability Optimizationmentioning

confidence: 99%

A page lifetime-aware scrubbing scheme for improving reliability of Flash-based SSD

Xie

Wang

et al. 2017

IEICE Electron. Express

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Solid-state drive (SSD) has gain prevalence in consumer and enterprise storage markets. However, its reliability is declining with the wearing of the Flash memory. The error correcting codes (ECCs) are generally applied in SSD to cope with bit errors caused by abrasion, however, the lifetime of pages in Flash is still limited to their fixed correctability. Due to different process and usage, the pages of Flash deteriorate in different speeds, which limited the service time of SSD. In order to prolong the lifetime of SSD, we proposed a Page Lifetime-aware Scrubbing (LaScrub) scheme to find dangerous pages which exist more bit errors. The simulation results show the proposed scheme is able to enhance the reliability of SSD. It gains 86% storage space compared with normal SSD at the same reliability requirement.

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“…Contrary to existing microcontroller solutions, such as [5], [6] and [7], the proposed design achieves greater performance for an equivalent overall system power, allowing faster data processing before returning to a low-power sleep state. The proposed Bellevue microcontroller is integrated into a 65nm ultra-low-power System-on-Chip (SoC), along with a CMOS image sensor (CIS) and power management unit (PMU) capable of energy harvesting.…”

Section: Introductionmentioning

confidence: 95%

Bellevue: A 50MHz variable-width SIMD 32bit microcontroller at 0.37V for processing-intensive wireless sensor nodes

Botman

Vos

Bernard

et al. 2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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In the context of wireless sensor nodes for the Internet-of-Things, there is a need for low-power highperformance computing cores for video monitoring applications. In this paper we present a custom 50MHz 32-bit microcontroller running at 0.37V built on a 65nm LP/GP CMOS process. Part of an energy-harvesting SoC with on-chip CMOS imager, it features adaptive voltage scaling, low-power 1.55µW sleep mode, and a variable-width SIMD pipeline and multiply/divide unit, achieving 7.7µW/MHz overall.Keywords-CMOS digital integrated circuits, VLSI, embedded microcontroller, near-threshold/subthreshold logic, system-on-chip (SoC), ultralow power, ultralow voltage, variability mitigation.

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A 200mV 32b subthreshold processor with adaptive supply voltage control

Cited by 21 publications

References 5 publications

An optimized reference current detection method for active power filter

An optimized reference current detection method for active power filter

A page lifetime-aware scrubbing scheme for improving reliability of Flash-based SSD

Bellevue: A 50MHz variable-width SIMD 32bit microcontroller at 0.37V for processing-intensive wireless sensor nodes

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