A 200 mW 3.3 V CMOS color camera IC producing 352×288 24 b video at 30 frames/s

Loinaz, M.J.; Singh, K.; Blanksby, Andrew; Inglis, D.; Azadet, K.; Ackland, B.

doi:10.1109/isscc.1998.672419

Cited by 24 publications

(19 citation statements)

References 17 publications

(32 reference statements)

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“…It can be used in the high-resolution applications by keeping the value of equal to 1.8 V or slightly smaller than 1.8 V. The measurement results of the proposed CIF OPAPS CMOS imager with the value of equal to 1.79 V are summarized in Table III, where the corresponding measurement results of the PAPS [4] and APS [18] CMOS imager are also given for comparisons. The dark current in the OPAPS CMOS imager is equal to 82 pA cm which is smaller than that of the PAPS [4], APS [18], [19], and PPS CMOS imager. In addition, the optical dynamic range of 65 dB in the OPAPS CMOS imager is larger than that of the APS [18], [19] and PPS CMOS imagers because the dark current in the OPAPS structure is the smallest.…”

Section: Resultsmentioning

confidence: 99%

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Optimal design of CMOS pseudoactive pixel sensor (PAPS) structure for low-dark-current and large-array-size imager applications

Shih

2005

IEEE Sensors J.

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In this paper, a pixel structure called the optimal pseudoactive pixel sensor (OPAPS) is proposed and analyzed for the applications of CMOS imagers. The shared zero-biased-buffer in the pixel is used to suppress both dark current of photodiode and leakage current of pixel switches by keeping both biases of photodiode and parasitic pn junctions in the pixel bus at zero voltage or near zero voltage. The factor of photocurrent-to-dark-current ratio per pixel area (PDRPA) is defined to characterize the performance of the OPAPS structure. It is found that a zero-biased-buffer shared by four pixels can achieve the highest PDRPA. In addition, the column sampling circuits and output correlated double sampling circuits are also used to suppress fixed-pattern noise, clock feedthrough noise, and channel charge injection. An experimental chip of the proposed OPAPS CMOS imager with the format of 352 288 (CIF) has been designed and fabricated by using 0.25-m single-poly-five-level-metal (1P5M) -well CMOS process. In the fabricated CMOS imager, one shared zero-biased-buffer is used for four pixels where the PDRPA is equal to 47.29 m 2 . The fabricated OPAPS CMOS imager has a pixel size of 8.2 8.2 m, fill factor of 42%, and chip size of 3630 3390 m. Moreover, the measured maximum frame rate is 30 frames/s and the dark current is 82 pA cm 2 . Additionally, the measured optical dynamic range is 65 dB. It is found that the proposed OPAPS structure has lower dark current and higher optical dynamic range as compared with the active pixel sensor (APS) and the conventional passive pixel sensor (PPS). Thus, the proposed OPAPS structure has high potential for the applications of high-quality and large-array-size CMOS imagers.Index Terms-CMOS imagers, dark current, optimal pseudoactive pixel sensor (OPAPS), photodiode, pn junctions.

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Section: Resultsmentioning

confidence: 99%

“…The dark current in the OPAPS CMOS imager is equal to 82 pA cm which is smaller than that of the PAPS [4], APS [18], [19], and PPS CMOS imager. In addition, the optical dynamic range of 65 dB in the OPAPS CMOS imager is larger than that of the APS [18], [19] and PPS CMOS imagers because the dark current in the OPAPS structure is the smallest.…”

Section: Resultsmentioning

confidence: 99%

Optimal design of CMOS pseudoactive pixel sensor (PAPS) structure for low-dark-current and large-array-size imager applications

Shih

2005

IEEE Sensors J.

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“…The most important advantage of the singleended differential pair is a reduction of the required chip area by operating the MOS transistor in the triode region. The required area is reduced by a factor of about 1.5 compared with conventional SEDP [8]. On the other hand the area of the proposed CDS circuit has reduce to the half of the conventional CDS because the two spur tracks of the conventional CDS has been incorporated.…”

Section: Reduced-area Low-power and Low-noise Considerationmentioning

confidence: 99%

“…Active pixel architectures are compatible with correlated-double sampling (CDS) techniques that have proven effective in reducing the readout noise [8]. The readout noise is reduced by reading out the pixel twice, once for the signal and once for the reset voltage, and the difference between these two values is taken as the signal value.…”

Section: Introductionmentioning

confidence: 99%

Principle of simple correlated double sampling and its reduced-area low-noise low-power circuit realization

Jin

2010

Analog Integr Circ Sig Process

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In this paper a simple block diagram of the simple and low-power correlated double sampling (CDS) is proposed suppressing the readout noise of CMOS active pixel sensor such as the kT/C noise, the 1/f noise and the fixed pattern noise. The principle of the simple CDS is described, analyzed and simulated. Based on the simple and low-power CDS principle a reduced-area, low-power and low-noise CDS circuit for CMOS APS is realized. For one spur track of the conventional CDS has saved and the low-power single-ended difference pair is used to finish the difference and amplified function, the area of the pixel cell with proposed CDS is reduced by a factor of above 2. Based on the standard TSMC 0.6 lm process the Hspice simulation results show that the active pixel cell with proposed CDS achieves a low power dissipation of 73.96 lW, the noise bandwidth of about 100 kHz, and the total output noise voltage of less than 4:45 nV ffiffiffiffiffiffi Hz p in the noise bandwidth.

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“…New technologies provide the potential for integrating a significant amount of VLSI electronics into a single chip, greatly reducing the cost, power consumption, and size of the camera [1][2][3][4]. By exploiting these advantages, innovative CMOS sensors have been developed and have demonstrated fabrication cost reduction, low power consumption, and size reduction of the camera [5][6][7].…”

Section: Introductionmentioning

confidence: 99%

A high speed programmable focal-plane SIMD vision chip

Ginhac

Dubois

Heyrman

et al. 2009

Analog Integr Circ Sig Process

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A high speed analog VLSI image acquisition and low-level image processing system is presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Each pixel include a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a fourquadrant multiplier architecture. A 64 9 64 pixel proof-ofconcept chip was fabricated in a 0.35 lm standard CMOS process, with a pixel size of 35 lm 9 35 lm. The chip can capture raw images up to 10,000 fps and runs low-level image processing at a framerate of 2,000-5,000 fps.

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A 200 mW 3.3 V CMOS color camera IC producing 352×288 24 b video at 30 frames/s

Cited by 24 publications

References 17 publications

Optimal design of CMOS pseudoactive pixel sensor (PAPS) structure for low-dark-current and large-array-size imager applications

Optimal design of CMOS pseudoactive pixel sensor (PAPS) structure for low-dark-current and large-array-size imager applications

Principle of simple correlated double sampling and its reduced-area low-noise low-power circuit realization

A high speed programmable focal-plane SIMD vision chip

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