Principle of simple correlated double sampling and its reduced-area low-noise low-power circuit realization

Abstract

In this paper a simple block diagram of the simple and low-power correlated double sampling (CDS) is proposed suppressing the readout noise of CMOS active pixel sensor such as the kT/C noise, the 1/f noise and the fixed pattern noise. The principle of the simple CDS is described, analyzed and simulated. Based on the simple and low-power CDS principle a reduced-area, low-power and low-noise CDS circuit for CMOS APS is realized. For one spur track of the conventional CDS has saved and the low-power single-ended difference pair is used to finish the difference and amplified function, the area of the pixel cell with proposed CDS is reduced by a factor of above 2. Based on the standard TSMC 0.6 lm process the Hspice simulation results show that the active pixel cell with proposed CDS achieves a low power dissipation of 73.96 lW, the noise bandwidth of about 100 kHz, and the total output noise voltage of less than 4:45 nV ffiffiffiffiffiffi Hz p in the noise bandwidth.

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