A 200-MSPS 6-bit flash ADC in 0.6-μm CMOS

Dalton, D.; Spalding, G.; Reyhani, Hooman; Murphy, Thomas E.; Deevy, Ken; Walsh, M.; Griffin, Pat

doi:10.1109/82.735355

Cited by 24 publications

(5 citation statements)

References 12 publications

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“…The fat tree encoder consumes more area than the proposed ROM encoder. Dalton et al [6] developed a 0.6µm 6-bit flash ADC at a relatively low speed of 200 MHz. Choi et al [7] implemented a 1.3 GHz A/D converter in 0.35µm CMOS technology.…”

Section: Introductionmentioning

confidence: 99%

High speed flash analog-to-digital converter

Abed

Nerurkar

2005

48th Midwest Symposium on Circuits and Systems, 2005.

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In this paper, we design a pipelined flash ADC to achieve high speed of 2 GHz in 0.18 µm CMOS technology using Cadence design tools. We design a high speed track and hold and a novel thermometer to binary encoder. We considered several approaches to design the track and hold circuit, such as buffered track and hold, switched capacitor track and hold, and single tail track and hold. These circuits are slower or have stability problems. We have used a current mode dual array track and hold, which is not only stable but also ensures good performance at 2 GHz. The thermometer to binary encoder can be designed using fat tree encoder, differential cascade voltage switch using pass gate encoder and ROM encoder with pass gates. We implement a novel encoder, which has advantages of high speed and hardware reduction over existing encoder circuits. A clocked DCVSPG XOR gate and a quantum voltage comparator are also used to improve the speed of the proposed flash ADC.

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Section: Introductionmentioning

confidence: 99%

High speed flash analog-to-digital converter

Abed

Nerurkar

2005

48th Midwest Symposium on Circuits and Systems, 2005.

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“…Technology Power Dissipation Proposed CMOS 0.18µm 36.98mW 6-bit TIQ [2] CMOS 0.25 µm 59.91mW 6-bit Flash [5] GaAs 0.5 µm 970mW 6-bt Flash [7] CMOS 0.6 µm 380mW 6-bit Flash [8] CMOS 0.4 µm 400mW 6-bit Flash [9] CMOS 0.6 µm 330mW Table 1. The proposed ADC power dissipation in comparison to other ADCs in the literature.…”

Section: Adcsmentioning

confidence: 99%

“…The output of the comparator is logic 1 or logic 0 depending on the applied input voltage. In the conventional differential voltage comparator [8,9], the transistor sizes are matched and the input V b is taken from V ref generated by the resistor ladder circuit.…”

Section: Introductionmentioning

confidence: 99%

An approach to design Flash Analog to Digital Converter for High Speed and Low power Applications

Rajeswari¹

2012

VLSICS

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“…To achieve good performance metrics over the whole input-range the bandwidth of the pre-amplifier must exceed the highest input frequency by almost a factor of 5 [l]. This is due to the problem of variable signal delay caused by the parallel structure of the different comparators (also called dispersion [4]). This is an inherent problem of flash A/D converters without front-end sample-and-hold.…”

Section: Building Blocks a Resistive Reference Ladder And Pre-amplijiermentioning

confidence: 99%

“…Therefore, to achieve a good performance at high frequencies the problem of metastability must be tackled. Flash-type architectures are typically the simplest and fastest structures that can be used to implement these very high-speed An> converters [1] [2][3] [4]. Figure 1 shows the detail& block diagram of the implemented flash A/D converter.…”

Section: Introductionmentioning

confidence: 99%

A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction

Uyttenhove

Marques

Steyaert

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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In this paper, a 6-bit CMOS analog-to-digital converter (An>) with a maximum acquisition speed of 1 GHz is presented. The problem of meta-stability has got special attention in this design, since this problem degrades the Spurious-Free Dynamic Range (SFDR) at high sampling frequencies. Measured SNDR (Signal to noise plus distortion) is over 30 dB at SOOMHz clock and f,N = 141 kHz. The measured SFDR for input frequencies up to 250 MHz is over 3OdB. The chip has been processed in a standard 0.35pm CMOS technology with double poly and occupies an active area of 0.8 mm2. IntroductionHigh-speed A/D converters used in automated test equipment, oscilloscopes and in digital data reading (e.g. hard disk drives and DVD) require very high sampling speeds, whereas resolutions as low as 6 bit are sufficient. Also, the enhanced capability of digital signal processing (DSP) circuits pushes the design of A/D converters towards ever-increasing sampling speeds. Not only the sampling speed is going up, also the maximum input frequency which has to be converted increases. Therefore, bandwidth-, distortion-and error rate-specifications are of utmost importance. Error rate is an aspect in the design of high-speed A/D converters which is often overlooked or underestimated. When the error rate is extremely high, the digitized waveform appears to disintegrate and the signalto-noise ratio (SNR) deteriorates rapidly. Since the error rate increases exponentially with the acquisition frequency, the metastability errors might increase by orders of magnitude for very high speed converters. Therefore, to achieve a good performance at high frequencies the problem of metastability must be tackled. Flash-type architectures are typically the simplest and fastest structures that can be used to implement these very

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A 200-MSPS 6-bit flash ADC in 0.6-μm CMOS

Cited by 24 publications

References 12 publications

High speed flash analog-to-digital converter

High speed flash analog-to-digital converter

An approach to design Flash Analog to Digital Converter for High Speed and Low power Applications

A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction

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