A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction

Abstract

In this paper, a 6-bit CMOS analog-to-digital converter (An>) with a maximum acquisition speed of 1 GHz is presented. The problem of meta-stability has got special attention in this design, since this problem degrades the Spurious-Free Dynamic Range (SFDR) at high sampling frequencies. Measured SNDR (Signal to noise plus distortion) is over 30 dB at SOOMHz clock and f,N = 141 kHz. The measured SFDR for input frequencies up to 250 MHz is over 3OdB. The chip has been processed in a standard 0.35pm CMOS technology with double poly and occupies an active area of 0.8 mm2. IntroductionHigh-speed A/D converters used in automated test equipment, oscilloscopes and in digital data reading (e.g. hard disk drives and DVD) require very high sampling speeds, whereas resolutions as low as 6 bit are sufficient. Also, the enhanced capability of digital signal processing (DSP) circuits pushes the design of A/D converters towards ever-increasing sampling speeds. Not only the sampling speed is going up, also the maximum input frequency which has to be converted increases. Therefore, bandwidth-, distortion-and error rate-specifications are of utmost importance. Error rate is an aspect in the design of high-speed A/D converters which is often overlooked or underestimated. When the error rate is extremely high, the digitized waveform appears to disintegrate and the signalto-noise ratio (SNR) deteriorates rapidly. Since the error rate increases exponentially with the acquisition frequency, the metastability errors might increase by orders of magnitude for very high speed converters. Therefore, to achieve a good performance at high frequencies the problem of metastability must be tackled. Flash-type architectures are typically the simplest and fastest structures that can be used to implement these very

A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip

“…In [16], an average termination circuit has been proposed to reduce power consumption. The problem of metastability at high sampling speeds has been addressed in [19]. Little attention has been given to the SoC integration problem faced by ADCs today.…”

A variability tolerant system-on-chip ready nano-CMOS analogue-to-digital converter

“…An average termination circuit has been proposed by Scholtens and Vertregt (2002) to reduce power consumption. The metastability problem at high sampling speeds has been addressed in Uyttenhove and Steyaert (2000). The SoC integration problem faced by ADCs has not been given sufficient attention.…”

Thermometer-to-binary decoders for flash analog-to-digital converters

“…The row decoder can be realized by, e.g., a number of 2-input NAND gates, where one input to each NAND gate is inverted. This type of row decoder selects multiple rows if a bubble error occurs, which introduces large errors in the output of the decoder [3], [4]. Considering single bubble errors only, these errors can be corrected by using 3-input NAND gates, as shown in Fig.…”

“…The sampling time uncertainty is therefore modeled as an offset voltage on the input of the comparators, given by (4). This model was used in the MATLAB simulations of a flash ADC with the four different decoders, i.e., the ROM decoder with 3-input NAND gates for bubble error correction, the ones-counter decoder, the MUX-based decoder, and the 4-level folded Wallace tree decoder.…”