A 200-MHz CMOS x/sin(x) digital filter for compensating D/A converter frequency response distortion

Lin, Tungyou; Samulei, H.

doi:10.1109/4.84945

Cited by 33 publications

(8 citation statements)

References 12 publications

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“…The total number of adders/subtractors, including the scale factor, to implement the entire analysis filter bank is 85. Recently there have been several high-speed VLSI single-chip implementations of CSD FIR filters [16], [17]. In [17] a 64-tap CSD FIR linear-phase filter, working at video rate, has been implemented on a single chip.…”

Section: The Optimization Algorithmmentioning

confidence: 99%

The design of low-complexity in linear-phase FIR filter banks using powers-of-two coefficients with an application to subband image coding

Horng

Samueli

Wilson³

1991

IEEE Trans. Circuits Syst. Video Technol.

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An optimization technique is presented for the design of multiplierless two-channel linear-phase finite-duration impulse-response (FIR) filter banks. It is shown to yield filter banks with good filtering performance and nearly perfect signal reconstruction. The design employs filters whose coefficients are represented by a canonic signed-digit (CSD) code. When applied to subband image coding this technique provides an easy way to design low-complexity analysis/synthesis filter banks for highperformance codecs. Examples concerning filter design and the application of such filters to subband image coding are given.

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Section: The Optimization Algorithmmentioning

confidence: 99%

The design of low-complexity in linear-phase FIR filter banks using powers-of-two coefficients with an application to subband image coding

Horng

Samueli

Wilson³

1991

IEEE Trans. Circuits Syst. Video Technol.

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“…Also, their latency should be low and not proportional to the number of filter taps. The scheme mostly used for the implementation of FIR filters, either in direct or in transposed form, is based on a chain of multiplier-accumulators [1][2][3]. Such a scheme, converted in pipelined form has been presented in the bibliography [4].…”

Section: Introductionmentioning

confidence: 99%

A New Low Latency Parallel FIR Filter Scheme

Kalivas

Vassilakis

Meletis

et al. 2005

J VLSI Sign Process Syst Sign Image Video Technol

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A new array type parallel scheme for an FIR digital filter is presented in this paper. The proposed scheme is based on the structure of the carry-save array multiplier where each cell implements the computation of an FIR filter at the bit-level. This structure leads to latency independent of the number of the filter taps. The proposed scheme is pipelined at the bit-level, is systolic at the cell-level and requires less hardware than other schemes based on discrete multipliers.

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“…The use of approximated values of the coefficients does not distort the transfer function much [3]. By representing the 11 coefficients ho -hlo in CSD form, all multiplications are replaced by at most 2 additions/subtractions of shifted data words (see Fig 1).…”

Section: Constant Coefficient Fir Filtermentioning

confidence: 99%

“…However, there are techniques to avoid the use of multipliers for constant coefficient filters. Using Canonical Signed-Digit (CSD) representation [3], multiplications are realised with minimal hardware through the use of a few shift-and-add's. This made desi nin of an entire 11-tap FIR filter possible on a singfe F#GA part.…”

Section: Introductionmentioning

confidence: 99%