2020
DOI: 10.1109/tcsi.2020.3007952
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A −20 dBm Passive UHF RFID Tag IC With MTP NVM in 0.13-μm Standard CMOS Process

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Cited by 7 publications
(8 citation statements)
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“…By comparing with repotted data in the references, it can be seen that the average power consumption of this design is 1/3000 of [4], 1/167 of [5], 1/294 of [6], and 1/3 of [7], and the average power consumption level of this demodulator is much lower than ones reported in the references. For passive UHF RFID, the ultra-low-power demodulator offers significant cost savings, high reliability and high noise immunity, making the demodulator more suitable for today's smart home and IoT detection.…”
Section: Low Power Verificationmentioning
confidence: 79%
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“…By comparing with repotted data in the references, it can be seen that the average power consumption of this design is 1/3000 of [4], 1/167 of [5], 1/294 of [6], and 1/3 of [7], and the average power consumption level of this demodulator is much lower than ones reported in the references. For passive UHF RFID, the ultra-low-power demodulator offers significant cost savings, high reliability and high noise immunity, making the demodulator more suitable for today's smart home and IoT detection.…”
Section: Low Power Verificationmentioning
confidence: 79%
“…Compared with the data given in the references, the power consumption value of this design is about one hundredth of the power consumption value given in the references [4][5][6] and the power consumption value of this design is about one third of the power consumption value given in the reference [7]. This paper gives specific data comparisons in Section 3.2 [8][9][10].…”
mentioning
confidence: 70%
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“…EEPROM can perform memory read and write operations. Still, because it requires a special process and a multilayer mask, a differential structure MTP memory cell compatible with the standard CMOS process is designed for these deficiencies in this paper concerning the structure in literature [3].…”
Section: System Architecture and Storage Unitsmentioning
confidence: 99%
“…e simulation result is shown as the solid line in the above figure by setting the voltage at the MC terminal to 0-3.5 V and setting the voltage at the MT terminal to zero. e other process is reversed, setting the voltage at the MT terminal to 0-3.5 V and setting the bias voltage at the MC terminal to zero [3]. e simulation result is shown as the dashed line in the above figure . When the voltage at the MC side of the control terminal changes from 0 to 3.5 V without adding the bias voltage at the MT side, it can be seen that the voltage of the floating gate also increases, and the other process is similar.…”
Section: Floating Grid State Analysismentioning
confidence: 99%