A 2$\,\times\,$25-Gb/s Receiver With 2:5 DMUX for 100-Gb/s Ethernet

Bae

2017

Sensors

The bandwidth requirement of wireline communications has increased exponentially because of the ever-increasing demand for data centers and high-performance computing systems. However, it becomes difficult to satisfy the requirement with legacy electrical links which suffer from frequency-dependent losses due to skin effects, dielectric losses, channel reflections, and crosstalk, resulting in a severe bandwidth limitation. In order to overcome this challenge, it is necessary to introduce optical communication technology, which has been mainly used for long-reach communications, such as long-haul networks and metropolitan area networks, to the medium- and short-reach communication systems. However, there still remain important issues to be resolved to facilitate the adoption of the optical technologies. The most critical challenges are the energy efficiency and the cost competitiveness as compared to the legacy copper-based electrical communications. One possible solution is silicon photonics which has long been investigated by a number of research groups. Despite inherent incompatibility of silicon with the photonic world, silicon photonics is promising and is the only solution that can leverage the mature complementary metal-oxide-semiconductor (CMOS) technologies. Silicon photonics can be utilized in not only wireline communications but also countless sensor applications. This paper introduces a brief review of silicon photonics first and subsequently describes the history, overview, and categorization of the CMOS IC technology for high-speed photo-detection without enumerating the complex circuital expressions and terminologies.

Section: Clock and Data Recovery (Cdr) Circuitsmentioning

confidence: 99%

Section: Clock and Data Recovery (Cdr) Circuitsmentioning

confidence: 99%

Section: Clock and Data Recovery (Cdr) Circuitsmentioning

confidence: 99%

See 1 more Smart Citation

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection

Bae

2017

Sensors

“…Since this conversion requires large-scale and high-speed electrical circuits such as a serializer=deserializer, clock data recovery are causing problems, namely, large power consumption and time delay. [1][2][3] To solve these problems, an optical burst switching system [4][5][6][7][8] and an optical packet switching system, [9][10][11][12][13] which do not require OEO conversion, have been studied to realize high-speed, compact, and lowpower optical communication.…”

Section: Introductionmentioning

confidence: 99%

High-speed and long-term wavelength stabilization of tunable distributed amplification distributed feedback laser after laser activation with feedforward and feedback control

Fukuda

Yamaguchi

Kuboki

et al. 2018

Jpn. J. Appl. Phys.

To manage recent exponentially increasing data traffic, optical-to-optical burst switching and packet switching systems have been attracting much attention because they do not require an optical-to-electrical and an electrical-to-optical conversions. These systems require high-speed optical switches with a large number of input/output ports. As a candidate for the optical switch, we have focused on the combination of wavelength tunable lasers and an arrayed waveguide grating router, and studied the tunable distributed amplification distributed feedback (TDA-DFB) lasers for the optical switch. Previously, our derived feedforward current control achieved high-speed wavelength switching at a single laser in six-arrayed TDA-DFB lasers. For larger-scale optical switching, wavelength switching from a laser to another in an array is required to cover a wide tunable range. In this study, we develop a novel current control model and successfully stabilize the wavelength immediately after laser activation, which would enable high-speed switching between different lasers. Furthermore, we demonstrate the combination of feedforward and feedback controls for high-speed switching with long-term stability.

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

“…1 shows the architecture of a PLL-based full-rate CDR architecture which incorporates a full-rate BBPD, a retiming circuit, a V-I converter, a voltage controlled oscillator (VCO), a clock buffer and a loop filter. The main power consuming components in a PLL-based CDR are the high-speed phase detector and retiming circuit, as well as the clock buffer which needs to drive large capacitive loads presented by the phase detector and retiming circuit [3][4].…”

Section: Introductionmentioning

confidence: 99%

A low-power 28 Gb/s CDR using artificial lc transmission line technique in 65 nm CMOS

Guo

et al. 2014

This paper presents a low-power 28 Gb/s PLLbased clock and data recovery circuit in 65 nm CMOS technology. The artificial LC transmission line technique is proposed to be used in the full-rate bang-bang phase detector to reduce the number of D-latches and save power consumption by 42.8% compared with the conventional phase detector design. By using the transmission line technique, the retiming circuit is merged into the phase detector, which further saves power of the data retiming circuit. The compact phase detector with built-in retiming circuit also alleviates the capacitive loading of and saves corresponding power consumed by the clock buffer. In addition, the artificial LC transmission line is proposed to be used in the clock buffer to drive the distributed capacitive loads presented by separate D-latch and save power consumption by 50% compared with the conventional inductive peaking clock buffer. The total power consumption of the CDR is 35 mW from a 1.1 V supply. Keywords-Clock and data recovery (CDR); low-power; transmission line; phase-locked loop (PLL)