A 2 Tb/s 6&lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$\,\times\,$&lt;/tex&gt; &lt;/formula&gt;4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS

Salihundam, Praveen; Jain, Shailendra; Jacob, Tiju; Kumar, Sachin; Erraguntla, Vasantha; Hoskote, Yatin; Muraleedharan, V. R.; Ruhl, G.; Borkar, Nitin

doi:10.1109/jssc.2011.2108121

Cited by 84 publications

(4 citation statements)

References 17 publications

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“…The fundamental packet switching NoC requires the implementation of lengthy pipelines within routers [ 29 ], as shown in Figure 4 a. This is due to the inclusion of buffers and virtual channels.…”

Section: The Proposed Architecturementioning

confidence: 99%

“…The processes of writing and reading data from buffers are time-consuming. In a general sense, the process of packet switching typically involves the execution of seven distinct phases [ 29 ]. The following components are included: Buffer Write (BW), Route Compute (RC), Virtual Channel Allocation (VA), Switch Allocation (SA), Buffer Read (BR), Switch Traversal (ST), and Link Traversal (LT).…”

Section: The Proposed Architecturementioning

confidence: 99%

“…BW is short for buffer write, RC for reserve channel, VA for VC allocation, SA for switch allocation, BR for buffer read, ST for switch traversal, and LT for link traversal. ( a ) For the VC router [ 29 ]. ( b ) For the PaCHNOC router.…”

Section: Figurementioning

confidence: 99%

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PaCHNOC: Packet and Circuit Hybrid Switching NoC for Real-Time Parallel Stream Signal Processing

Hao,

Zhang,

Zhou

et al. 2024

Micromachines

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Real-time heterogeneous parallel embedded digital signal processor (DSP) systems process multiple data streams in parallel in a stringent time interval. This type of system on chip (SoC) requires the network on chip (NoC) to establish multiple symbiotic parallel data transmission paths with ultra-low transmission latency in real time. Our early NoC research PCCNOC meets this need. The PCCNOC uses packet routing to establish and lock a transmission circuit, so that PCCNOC is perfectly suitable for ultra-low latency and high-bandwidth transmission of long data packets. However, a parallel multi-data stream DSP system also needs to transmit roughly the same number of short data packets for job configuration and job execution status reports. While transferring short data packets, the link establishment routing delay of short data packets becomes relatively obvious. Our further research, thus, introduced PaCHNOC, a hybrid NoC in which long data packets are transmitted through a circuit established and locked by routing, and short data packets are attached to the routing packet and the transmission is completed during the routing process, thus avoiding the PCCNOC setup delay. Simulation shows that PaCHNOC performs well in supporting real-time heterogeneous parallel embedded DSP systems and achieves overall latency reduction 65% compared with related works. Finally, we used PaCHNOC in the baseband subsystem of a real 5G base station, which proved that our research is the best NoC for baseband subsystem of 5G base stations, which reduce 31% comprehensive latency in comparison to related works.

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Section: The Proposed Architecturementioning

confidence: 99%

Section: The Proposed Architecturementioning

confidence: 99%

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PaCHNOC: Packet and Circuit Hybrid Switching NoC for Real-Time Parallel Stream Signal Processing

Hao,

Zhang,

Zhou

et al. 2024

Micromachines

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“…A large number of on-chip many-core systems have been designed for a wide range of applications, including scientific computing, the Internet-based services, the newly emerging applications of recognition, mining, and synthesis (RMS) [1], among many others [2]. One of the key components of an on-chip many-core system is its on-chip network (OCN) or network-on-chip (NoC), which has to provide efficient communication bandwidths for the processor cores and other resources with low latency and low power.…”

Section: Introductionmentioning

confidence: 99%

On self-tuning networks-on-chip for dynamic network-flow dominance adaptation

Wang

Yang

Jiang

et al. 2014

ACM Trans. Embed. Comput. Syst.

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Modern networks-on-chip (NoC) systems are required to handle complex run-time traffic patterns and unprecedented applications. Data traffics of these applications are difficult to be fully comprehended at design-time so as to optimize the network design. However, it has been discovered that the majority data flows in a network are dominated by less than 10% of the specific pathways. In this paper, we introduce a method that is capable of identifying critical pathways in a network at run-time and, then, can dynamically reconfigure the network to optimize for the network performance subjected to the identified dominated flows. An online learning and analysis scheme is employed to quickly discover the emerged dominated traffic flows and provides a statistical traffic prediction using regression analysis. The architecture of a self-tuning network is also discussed which can be reconfigured by setting up the identified point-to-point paths for the dominance data flows in large traffic volumes. The merits of this new approach are experimentally demonstrated using comprehensive NoC simulators. Compared to the conventional network architectures over a range of realistic applications, the proposed self-tuning network approach can effectively reduce the latency and power consumption by as much as 25% and 24%, respectively. We also evaluated the configuration time and additional hardware cost. This new approach demonstrates the capability of an adaptive NoC to handle more complex and dynamic applications.

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