Fundamental Limits on Run-Time Power Management Algorithms for MPSoCs

Garg, Siddharth; Marculescu, Diana; Mărculescu, Radu

doi:10.1007/978-1-4614-4975-1_1

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Power Reduction Techniques1

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“…As supply voltage of CMOS circuit decreasing from 5V , 3.3V to 1V and below from one technology node to the next, the dynamic voltage range that can be selected by DVFS becomes much narrower now comparing to the days when DVFS was just proposed. In [102] and [103], the technology-driven limitations of DVFS techniques were studied. It was pointed out that the dynamic range of supply voltage greatly influences the effectiveness of DVFS, and the larger process variation induced by advanced technology node will significantly reduce the controllability of DVFS schemes.…”

Section: Power Reduction Techniquesmentioning

confidence: 99%