A 2 K-gate high performance merged complementary BiCMOS gate array

Abstract

Using high performance merged complementary BiCMOS circuit structure, a 2K-gate BiCMOS gate array master slice and its unit cell library have been designed and created by 2 P m rules. On this master slice, a double 64 bits high speed shift register has also been customized. A intemal gate delay of the gate array is 0.65ns(typical). The operating frequency of the custom IC is more than 1OOMHz.