A 2-GHz 32-bit ROM-based direct-digital frequency synthesizer in 0.13 μm CMOS

Guo, Xuan; Wu, Danyu; Zhou, Lei; Liu, Huasen; Wu, Jin; Liu, Xinyu

doi:10.1007/s10470-017-1070-8

Cited by 4 publications

(4 citation statements)

References 25 publications

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“…It was introduced to lower the consumption, with still a constraint in the clock frequency up to only 230 MHz. A number of other successful implementations have come after [49][50][51][52][53][54][55][56][57][58][59][60][61][62][63]. Figure 16 shows the maximum clock frequency versus consumption for different RF-DDFSs based on NL-DAC topologies for SiGe and GaAs technologies.…”

Section: Radio Frequency Ddfssmentioning

confidence: 99%

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Evolution Trends and Paradigms of Low Noise Frequency Synthesis and Signal Conversion Using Silicon Technologies

2022

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Silicon technologies for HF applications have been proven for more than two decades, and technologies have greatly evolved. Whether CMOS or BiCMOS technologies, the unique combination of radio frequency, baseband, and digital functions allow a very high level of integration. While it is possible to achieve fully integrated transceivers, the major advantages of these silicon technologies lie mainly in their unparalleled performance in the field of frequency synthesis and frequency conversion. We propose in this paper a review of the major results obtained on these RF components since the beginning of the 2000s, also considering the impact of the technology node. The back-end of line (BEOL) process on which depends the quality of microwave monolithic integrated circuits (MMICs) is briefly presented in the introductory part. If circuit performances are tightly bound to the active devices (i.e., the heterojunction bipolar transistor SiGe HBT or CMOS transistor), passive elements (i.e., quality factor of inductors and varactors, losses of transmission, or interconnection lines) as well as the definition of the substrate also play a major role. The core of the article is oriented toward the noise of synthesized signals and frequency conversion. Frequency synthesis is presented through the analog design of a voltage-controlled oscillator (VCO) or through the direct digital frequency synthesis (DDFS), for which respective figures of merit are presented and discussed in a second section. The spectral purity of the oscillators being decisive in the definition of the throughput of a link is approached through the comparison of different figures of merit (FoM) for a set of circuits achievements over the selected period. If the realization of free oscillators is closely bound to the phase-locked loop (PLL)-type control loop for VCOs, the DDFS solution provides more direct and more flexible alternative at first sight. Therefore, these two solutions are analyzed collectively. Finally, the oscillator integrated in the transmitter or receiver supplies the needed LO (local oscillator) power to the frequency mixer in the frequency conversion module: henceforth, the third part of this study focuses on high-frequency mixer realizations. We thus consider this LO power in some advanced figure of merit mentioned in the second section. The design trade-off of the mixer is presented in an approach combining LO (conversion gain, channel isolation, and phase noise) and RF (HF noise figure and channel isolation) constraints. The final section provides a summary of the results and trends mentioned in the paper.

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Section: Radio Frequency Ddfssmentioning

confidence: 99%

“…Figure 17. Retained FoM (Equation (15)) versus year and month of publication[45,[49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67]70,72,73,75].…”

mentioning

confidence: 99%

Evolution Trends and Paradigms of Low Noise Frequency Synthesis and Signal Conversion Using Silicon Technologies

2022

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“…The following Equation expresses the frequency of the sinusoid that appears at the DAC output for a traditional accumulator-based DDS [18]:…”

Section: Defects Of Traditional Ddsmentioning

confidence: 99%

An Accurate DDS Method Using Compound Frequency Tuning Word and Its FPGA Implementation

Yuqing

Tang

2018

Electronics

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Because of its high resolution, low cost, small volume, low power dissipation and less conversion time consumption, the direct digital synthesizer (DDS) method has been applied more and more in the fields of frequency synthesis and signal generation. However, only a limited number of precise frequency signals can be synthesized by the traditional DDS, for the reason that its accumulator modulus is fixed, and its frequency tuning word must be integer. In this paper, a precise DDS method using compound frequency tuning word is proposed, which improves the accuracy of synthesized signals at any frequency points on the premise of guaranteeing the stability of synthesized signals. In order to verify the effectiveness of the new method, a DDS frequency synthesizer based on FPGA is designed and implemented. Taking the rubidium atomic clock PRS10 as standard frequency source, the experiments shows that the frequency stability of the synthesized signal is better than 8.0 × 10−12/s, the relative frequency error is less than 4.8 × 10−12, and that the frequency accuracy is improved by three orders of magnitude compared with the traditional DDS method.

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“…Owing to these advantages, the DDFS method has been used in a wide range of applications such as radar, military equipment, medical devices, and aircraft [1]- [3]. However, the DDFS method has the critical drawback in high power consumption, causing the difficulty of using it in portable (battery-powered) devices [4], [5]. Since the DDFS conventionally uses readonly-memory (ROM) for signal generation, the required ROM size gets also significantly increased as the performance requirements of the synthesizer increases.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of Low Power and High SFDR Direct Digital Frequency Synthesizer

et al. 2020

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Due to the advantages of fast frequency shifting, continuous phase shifting, fine frequency resolution, large bandwidth, and excellent spectral purity, the direct digital frequency synthesis (DDFS) technique is attracting more attention than ever before. Although the DDFS suffer from high power consumption, recent researches on the development of the low power DDFS (LP-DDFS) increases the feasibility of applying the DDFS to portable devices. To further accelerate the use of LP-DDFS, a new LP-DDFS design to significantly improve power efficiency is proposed and analyzed in this paper. In the new design, the dominant spur by truncation errors causing performance degradation has been also thoroughly considered. Since the existing dithering techniques for the truncation error problems can cause the additional performance degradation due to the side effects such as frequency offset and SNDR deterioration, an enhanced dithering technique is also proposed in this paper. The proposed technique includes a frequency compensation circuit and thus minimizes the truncation errors in the LP-DDFS with the minimal additional power consumption and SNDR degradation. Both theoretical and experimental analysis are conducted to verify the proposed design, where a prototype chip is fabricated and measured. INDEX TERMS Direct digital frequency synthesizer (DDFS/DDS), dithering scheme, high spuriousfree dynamic range (SFDR), low power design, Phase accumulator (PACC), pseudo-random binary sequence (PRBS).

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A 2-GHz 32-bit ROM-based direct-digital frequency synthesizer in 0.13 μm CMOS

Cited by 4 publications

References 25 publications

Evolution Trends and Paradigms of Low Noise Frequency Synthesis and Signal Conversion Using Silicon Technologies

Evolution Trends and Paradigms of Low Noise Frequency Synthesis and Signal Conversion Using Silicon Technologies

An Accurate DDS Method Using Compound Frequency Tuning Word and Its FPGA Implementation

Design and Analysis of Low Power and High SFDR Direct Digital Frequency Synthesizer

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