A 2.9ns random access cycle embedded DRAM with a destructive-read

Hwang, C.; Kirihata, T.; Wordernan, M.; Fifield, J.A.; Storaska, D.; Pontius, D.; Fredernan, G.; Ji, Bing; Tomashot, S.; Dhong, S.H.

doi:10.1109/vlsic.2002.1015077

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A 2.9ns random access cycle embedded DRAM with a destructive-read

Cited by 10 publications

References 1 publication

A Low Power 128Mb Pseudo SRAM Using Hyper Destructive Read Architecture

A Low Power 128Mb Pseudo SRAM Using Hyper Destructive Read Architecture

Embedded memory in system-on-chip design: architecture and prototype implementation

Row-buffer decoupling: A case for low-latency DRAM microarchitecture

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