Abstract:This paper proposes a one-branch zero-IF receiver topology, which samples the I and Q signals of the modulated RF carrier with one signal path by means of a multiphase local oscillator. The suggested one-branch receiver works without matching problem, and it is also capable of cancelling out the flicker noise and DC-offset when the local oscillator is configured to the four-phase mode. The one-branch receiver saves much area and power compared with the traditional two-branch ones. All of the advantages above make the one-branch receiver topology a promising architectural candidate for low-power and low-cost RF CMOS receiver designs.The low-power and low-cost RF CMOS receivers have been gaining more and more importance in recent years, especially for the sensor network, medical implanted wireless link and RF ID applications [1][2][3][4][5][6] . The zero-IF receiver topology is one of the most popular choices. To eliminate the image noise, zero-IF RF CMOS receivers have to downconvert RF input signals with image-rejection-mixing(IRM) technology, which derives the I and Q signals with two signal paths [7] . Theoretically, the performance of the image rejection of an IRM receiver depends directly on the matching quality between two signal branches in the IRM receiver.Even though the RF CMOS zero-IF receiver requires no image rejection filters and can be realized with high integration level, the flicker noise and DC offsets are two critical drawbacks, which represent error components within the same band as the signal desired [8] . By using mixers with low flicker noise and feeding back the error signal to cancel out DC-offsets, the zero-IF receiver can be realized at the cost of area and power [9][10][11][12][13][14] . One of the most efficient ways is to develop a novel receiver topology without matching problem and cancel out the flicker noise and DC-offset mathematically. For this purpose, this paper suggests a one-branch zero-IF receiver topology, which derives I and Q signals from the modulated RF signal with one signal path by using multiphase local oscillator(LO).
Receiver topologyThe proposed multiphase-LO receiver includes 2-phase (2p)-LO receiver and 4-phase (4p)-LO receiver. Fig.1 shows the topology of the 2p-LO receiver. A special building block in the 2p-LO receiver is the clock generator, which creates Clk_1, Clk_2 and Clk_3 to synchronize the operation sequences of IQ-switching LO generator, integrator and A/D converter. The LNA amplifies the input RF signal, and its output f(t) is fed into the mixer. The IQ-switching LO generator generates the 2p-LO signal s(t), which, controlled by Clk_1, periodically skips its original phase between 0 and π/2. The mixer downconverts the RF signal to get the zero-IF signal m(t) by multiplying f(t) and s(t).where φ 0 is the initial phase of LO. m(t) is fed into the integrator, in which an integration will be performed periodically within time interval (t 0 , t 0 +T/2) and an output p(t)will be obtained. p(t) is fed into the A/D converter to generate digital o...