A 2.4-GHz RF sampling receiver front-end in 0.18-/spl mu/m CMOS

Jakonis, Darius; Folkesson, Kalle; Dbrowski, J.; Eriksson, Per; Svensson, Christer

doi:10.1109/jssc.2005.848027

Cited by 111 publications

(62 citation statements)

References 15 publications

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“…In other published works, the receivers based on subsampling were implemented experimentally for only fixed bands. Thus, low-noise subsampling implementations for the 2.1 GHz band [30] and for 2.4 GHz (IEEE 802.11a/g WLAN standards) [31] have been proposed. In [30], an IC receiver designed in 0.18 μm CMOS (complementary metal oxide semiconductor) was presented, the main goal of which was a tunable LC (inductor, capacitor) filter implementation.…”

Section: Comparison With Other Implemented Multi-standards Receiversmentioning

confidence: 99%

“…In [30], an IC receiver designed in 0.18 μm CMOS (complementary metal oxide semiconductor) was presented, the main goal of which was a tunable LC (inductor, capacitor) filter implementation. In [31], a 0.18 μm CMOS receiver represented the most complete subsampling receiver reference, due to the optimization performed for parameters, such as thermal noise level, jitter-induced noise and nonlinearity. Finally, there were also receivers based on subsampling for ultra wideband (UWB) applications, such the one in [32], which operates in the 3.1 -10.6 GHz band with low power consumption.…”

Section: Comparison With Other Implemented Multi-standards Receiversmentioning

confidence: 99%

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Subsampling Receivers with Applications to Software Defined Radio Systems

Oya¹,

Kwan²,

Chavero³

et al. 2012

Data Acquisition Applications

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Section: Comparison With Other Implemented Multi-standards Receiversmentioning

confidence: 99%

Section: Comparison With Other Implemented Multi-standards Receiversmentioning

confidence: 99%

Subsampling Receivers with Applications to Software Defined Radio Systems

Oya¹,

Kwan²,

Chavero³

et al. 2012

Data Acquisition Applications

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“…The cost effectiveness and the design reusability of the transmitter and receiver architecture became a key issue and the approaches based on the software radio (SR) paradigm [1] and RF sampling [2] begun to furnish viable solutions even for consumer applications. The acquisition and successive quantization of the received signal, indeed, allow a numerical manipulation of the signal with evident advantages in terms of re-configurability and adaptability of the receiver to different standards, most of all, when these operations are performable over a wide RF input frequency range covering several telecommunication standards.…”

Section: Introductionmentioning

confidence: 99%

“…At the state-of-the-art, the receiver architecture still relies on a preliminary down conversion to match the available ADCs and DSPs performances. As an alternative to the mixer, the sample & hold (S/H) mixer can perform the down conversion operation with comparable performances [2]. The resulting structures are usually referred as software defined radio (SDR) receivers.…”

Section: Introductionmentioning

confidence: 99%

A 12-bit track and hold amplifier for giga-sample applications

Cannone

Avitabile

2015

Analog Integr Circ Sig Process

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The paper presents a track-and-hold amplifier (THA), based on the switched emitter follower topology, suitable for emerging receivers architectures and data acquisition systems. The THA exploits four concurrent techniques, all described in the paper, which allow to reduce the hold-mode feedthrough; to attenuate the differential droop rate; to improve the linearity of the input buffer; and to optimize the third order harmonic distortion for RF sampling operation. The effectiveness of this novel approach is demonstrated using a low cost 0.35 lm SiGe technology. The THA core draws about 145 mA from 3.5 V supply. The THA provides a spurious-free dynamic range (SFDR) better than 72 dB when it is used for sampling an incoming signal of 0.9 V pp centered around 925 MHz at a sampling rate of 0.5 GS/s. The THA allows a max sampling frequency equal to 6 GS/s and a max input frequency equal to 2.5 GHz and provides a SFDR better than 50 dB in all the available working conditions.

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“…Recently, the feasibility of CMOS D-T radio receivers using RF sampling has been demonstrated for Bluetooth [1], GSM/GPRS [2] and WLAN [3]. As shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

On the Suitability of Discrete-Time Receivers for Software-Defined Radio

Klumperink

Nauta

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-CMOS radio receiver architectures, based on radio frequency (RF) sampling followed by discrete-time (D-T) signal processing via switched-capacitor circuits, have recently been proposed for dedicated radio standards. This paper explores the suitability of such D-T receivers for highly flexible softwaredefined radio (SDR) receivers. Via symbolic analysis and simulations we analyze the properties of D-T receivers, and show that at least three challenges exist to make a D-T receiver work for SDR: 1) the sampling clock frequency is related to the radio frequency, complicating baseband filter design; 2) a frequency-dependent phase shift is introduced by pseudoquadrature and pseudo-differential sampling; 3) the conversion gain of a charge sampling front-end is strongly frequencydependent. Compared to a mixer based radio receiver, extra costs are needed to solve these problems.

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A 2.4-GHz RF sampling receiver front-end in 0.18-/spl mu/m CMOS

Cited by 111 publications

References 15 publications

Subsampling Receivers with Applications to Software Defined Radio Systems

Subsampling Receivers with Applications to Software Defined Radio Systems

A 12-bit track and hold amplifier for giga-sample applications

On the Suitability of Discrete-Time Receivers for Software-Defined Radio

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