A 2.4-GHz frequency synthesizer based on process and temperature compensated ring ILFD

Vijayaraghavan, R.; Zhu, Kai; Islam, Syed K.

doi:10.1007/s10470-012-9993-6

Cited by 2 publications

(1 citation statement)

References 19 publications

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“…A differential cross-coupled LC oscillator topology such as Fig. 3 is selected since it is less sensitive to PVT, as well as to common-mode noise interferences [12,13]. An equal amount of bias is provided for both gates of the transistors.…”

Section: Lc Oscillator Based Vcomentioning

confidence: 99%

A temperature stabilized CMOS VCO

Sebastian

Sinha

2014

Analog Integr Circ Sig Process

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The established method of frequency drift compensation in voltage controlled oscillators (VCOs) resulting from temperature variance involves modulation of control voltage using a non-linear voltage internally generated. An innovative frequency drift compensation scheme for a VCO, based on amplitude control, is described in this paper. Two peak detectors are used to generate voltages representing positive and negative peaks of the sinusoidal driving an error amplifier. The amplifier output controls the delivery of transconductance accessible to the oscillator, thereby keeping the oscillation amplitude steady. Frequency stability has improved to 16 ppm/°C from an uncompensated value of 189 ppm/°C and is applicable where frequency stability requirements are not stringent, such as HS-USB and S-ATA. The temperature stabilized VCO at 2.4 GHz center frequency is prototyped using CMOS technology from ams AG (formerly austriamicrosystems AG). The result obtained from this study indicates that better frequency stability may be achievable if the traditional compensation scheme is preceded by amplitude control.

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Section: Lc Oscillator Based Vcomentioning

confidence: 99%

A temperature stabilized CMOS VCO

Sebastian

Sinha

2014

Analog Integr Circ Sig Process

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A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring Oscillator Frequency

Kumar

Nagulapalli

Vishvakarma

2022

J CIRCUIT SYST COMP

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Phase Locked Loop (PLL) is an on-chip clock generator for timing-centric electronic systems. Voltage Controlled Oscillator (VCO) is the key element for high-performance PLLs. A detailed qualitative explanation has been given to describe VCO operation. It is shown from simulation results that the variation of small signal transconductance ([Formula: see text]) is the main dominant source of frequency and gain ([Formula: see text]) variation in a VCO. In this work, simulation results for the conventional ring oscillator are presented which demonstrates [Formula: see text] times variation in [Formula: see text] across Process Voltage Temperature (PVT) corners. Such huge sensitivity to PVT is undesirable for high bandwidth PLL design. To mitigate this sensitivity, a constant-gm bias circuit is proposed in this paper, with a detailed mathematical analysis. A prototype of 4-stage ring oscillator with center frequency of 5[Formula: see text]GHz is developed in 65[Formula: see text]nm TSMC CMOS technology, and post-layout simulation results are carried out. Results show that maximum [Formula: see text] variation of 28% and frequency variation of 17% at a given control voltage. Temperature sensitivity has been decreased from 19.3% to 7% using the proposed biasing technique. Proposed solution consumes 2.4[Formula: see text]mW power from 1[Formula: see text]V power supply.

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A 2.4-GHz frequency synthesizer based on process and temperature compensated ring ILFD

Cited by 2 publications

References 19 publications

A temperature stabilized CMOS VCO

A temperature stabilized CMOS VCO

A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring Oscillator Frequency

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