A 2.4 GHz fractional-N PLL with a low-power true single-phase clock prescaler

Abstract

A 2.4 GHz fractional-N PLL implemented in 65-nm CMOS process is presented in this letter. A TSPC dual-modulus prescaler is proposed to reduce the PLL's power consumption by merging one of the branches of the true single-phase clocked (TSPC) D flip-flops. The measured synthesizer output frequency ranges from 2.16 to 2.7 GHz, and consumes 8 mW from a 1.3 V power supply. The in-band phase noise is −98 dBc/Hz at 100 kHz offset, and −115 dBc/Hz at 1 MHz offset at a carrier frequency of 2.438 GHz. The circuit achieves the RMS jitter of 0.86 ps and figure of merit of −230 dB, with the fractional spurs below −55 dBc.

A modified pulse swallow frequency divider for fractional-N PLL

“…4(a). It is a mixed-mode of synchronous logic and asynchronous logic [6,27,28]. When MC = 0, the synchronous logic cell divides the input signal by two, which then travels through the asynchronous divide-by-2 circuit, resulting in a total division ratio of 4.…”

“…The divide-by-4/5 dual-modulus prescaler consists of three DFF, namely DFF0, DFF1, and DFF2. The implemention of these DFFs use true-single phase clock (TSPC) structure, which reduce the power consumption [4,5,6,29,30]. The DFFs outputs are defined as qb 0 , q 1 , and q 2 , and the divider state is defined as "qb 0 q 1 q 2 ", where the next state is calculated using: qb 0 + = qb 0 ', q 1 + = qb 0 , and q 2 + = qb 2 *q 1 + q 2 *q 1 '.…”

“…As a crucial component of the fractional-N frequency synthesizer, the frequency divider puts forward higher requirements. Therefore, a high operating speed and low power consumption fractional-N frequency divider are highly desired [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20]. The working speed limitation of pulse swallow frequency divider is determined by the delay time of MC signal (τ MC ) [1,2,3,20,21,22,23,24,25,26].…”

A 0.7V 1.6mW fractional-N synthesizers for BLE RF transceiver in 40nm CMOS

“…The fractional-N RF synthesizer is essential to wireless communication systems. It is required to generate a low phase noise and low spur LO while achieving low power consumption [1,2,3,4,5,6,7,8]. Reducing the supply voltage is an effective way to reduce power consumption.…”

“…In addition, a high-swing gate-switching charge pump is applied to reduce the reference spur, in which a rail-to-rail master-slave operational trans-conductance amplifier (OTA) is applied to improve the current matching. The synthesizer is designed to meet the in-band phase noise requirement of less than −75, −80, −80 dBc/Hz at 1 KHz, 10 KHz, and 100 KHz offsets [3], respectively.…”