A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique

Kim, Hyunik; Kim, Yongjo; Kim, Tae-Ik; Ko, Hyung–Jong; Cho, Seonghwan

doi:10.1109/jssc.2017.2734910

Cited by 34 publications

(11 citation statements)

References 15 publications

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“…Also, the trade-off between the PLL's loop bandwidth and stability makes it challenging to generate wide-range output clock frequencies in a single integer-N PLL. Electronics 2022, 11, 261. https://doi.org/10.3390/electronics11020261 https://www.mdpi.com/journal/electronics Among various on-chip clock generators, multiplying delay-locked loops (MDLLs) can be considered as a way to implement the N/M-ratio frequency multiplication while improving the jitter performance with reduced loop bandwidth issues [4][5][6][7][8][9][10][11][12][13][14][15][16].…”

Section: Introductionmentioning

confidence: 99%

An N/M-Ratio All-Digital Clock Generator with a Pseudo-NMOS Comparator-Based Programmable Divider

Kim

2022

Electronics

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A multiplying delay-locked loop (MDLL)-based all-digital clock generator with a programmable N/M-ratio frequency multiplication capability for digital SoC is presented. The proposed digital MDLL provides programmable N/M-ratio frequency multiplication using a new high-speed Pseudo-NMOS comparator-based programmable divider with small area and low power consumption. The proposed MDLL clock generator can also provide a de-skew function by eliminating the phase offset problem caused by the propagation delay of the front divider in conventional N/M MDLL architectures. Fabricated in a 0.13-µm 1.2-V CMOS process, the proposed digital MDLL clock generates fully de-skewed output clock frequencies from 0.3 to 1.137 GHz with programmable N/M ratios of N = 1~32 and M = 1~16. It achieves a measured effective peak-to-peak jitter of 12 ps at 1.0 GHz when N/M = 8/1. It occupies an active area of only 0.034 mm2 and consumes a power of 10.3 mW at 1.0 GHz.

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Section: Introductionmentioning

confidence: 99%

An N/M-Ratio All-Digital Clock Generator with a Pseudo-NMOS Comparator-Based Programmable Divider

Kim

2022

Electronics

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“…Also, PLLs usually have relatively high jitter or phase noise characteristics. Recently, multiplying delay-locked loops (MDLLs) [11][12][13][14][15][16][17][18][19][20][24][25][26][27][28][29][30], a type of injection-locked voltage-controlled oscillators (VCOs), have received considerable attention as on-chip clock generators for digital ICs and highperformance system-on-chips (SoCs) owing to their excellent jitter and stability performance. A typical MDLL can generate an output frequency that is N times the input clock frequency, where N is an integer.…”

Section: Introductionmentioning

confidence: 99%

“…A typical MDLL can generate an output frequency that is N times the input clock frequency, where N is an integer. Digital MDLLs [11][12][13][14][15][16][17] are preferred in many applications to reduce the deterministic jitter (DJ) due to mismatch problems of analog components such as phase detectors (PDs) and charge pumps in addition to eliminating lock status loss problems during the power-down mode. Although an MDLL can reduce the integrated jitter by periodically injecting a clean reference clock, the jitter or phase noise performance rapidly degrades as the frequency multiplication factor N increases.…”

Section: Introductionmentioning

confidence: 99%

“…Although an MDLL can reduce the integrated jitter by periodically injecting a clean reference clock, the jitter or phase noise performance rapidly degrades as the frequency multiplication factor N increases. The problem of jitter accumulation with N values becomes more acute in digital MDLLs using a bang-bang phase detector (BBPD) and a digitally controlled multiplexed ring oscillator (MRO) [14,16,17]. When the digital MDLL is in the lock state, the nonlinearity characteristic of the BBPD and the finite resolution of the MRO cause the phase of the MDLL output clock to move back and forth on the reference clock edge.…”

Section: Introductionmentioning

confidence: 99%

“…The problem is that even though the DCW only changes by one LSB during a limit cycle, the integrated phase of the MDLL output clock moves by N × ∆t, where ∆t is the time resolution of the digitally controlled MRO. Consequently, as N increases or as the reference clock period (TREF) increases, the magnitude of deterministic jitter (DJ) of the digital MDLL rapidly increases in proportion to N. Therefore, designing a digital MDLL with a large N is difficult, and most digital MDLLs only have N = 32 or less [12][13][16][17]. To overcome this limitation, the digital MDLL introduced in [14] utilizes a scrambling time-to-digital converter (TDC) with a second-order delta-sigma modulator (DSM) to reduce the limit cycle period to 1/64 and achieve N = 128.…”

Section: Introductionmentioning

confidence: 99%

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A low-jitter 2.4 GHz all-digital MDLL with a dithering jitter reduction scheme for 256 times frequency multiplication

Park

Kim

2020

IEICE Electron. Express

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A new all-digital multiplying delay-locked loop (MDLL) based frequency multiplier architecture with a high frequency multiplication factor N of 256 is presented. The proposed MDLL utilizes a dithering jitter reduction scheme based on a delta-sigma modulation to achieve a low deterministic jitter and a large N factor. Additionally, a new stochastic phase detector is proposed to reduce static phase offset and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed all-digital MDLL generates 2.4-GHz output clock and achieves a peak-to-peak jitter of 6.47 ps with N = 256. It occupies an active area of 0.032 mm 2 and achieves a power efficiency of 0.875 mW/GHz.

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Low power 10T phase and frequency detector for high frequency phase locked loop

Rajalingam

Srinivasan²,

Jayakumar

et al. 2023

Int J Numerical Modelling

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The high‐frequency circuits used in communication systems significantly depend on the functioning of the Phase‐Locked Loop (PLL). The power consumption is traded with the performance in the high‐frequency PLL. The proposed robust Phase and Frequency Detector (PFD) has multiple benefits of low‐power and reliable functioning at high frequency. The PFD highly contributes to the stable performance of the PLL, and this work proposes a 10T PFD for low‐power. The proposed PFD employs Gate Diffusion Input (GDI) logic based D‐flip flop and the pass transistor logic in the reset path to reduce power consumption. The PFD uses only 10 transistors, enabling a faster reset path and consuming less power at high frequencies. The 10T PFD was designed using 90 nm CMOS PDKs and simulated using CADENCE Specter for functional verification and performance analysis. The 10T PFD achieved a reset time of 61.4 ps at 3 GHz alongside a power consumption of 189.2 nW. Also, the overall power consumption of PLL using the proposed PFD at 3 GHz was demonstrating the effectiveness of 10T PFD over other conventional PFDs.

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A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique

Cited by 34 publications

References 15 publications

An N/M-Ratio All-Digital Clock Generator with a Pseudo-NMOS Comparator-Based Programmable Divider

An N/M-Ratio All-Digital Clock Generator with a Pseudo-NMOS Comparator-Based Programmable Divider

A low-jitter 2.4 GHz all-digital MDLL with a dithering jitter reduction scheme for 256 times frequency multiplication

Low power 10T phase and frequency detector for high frequency phase locked loop

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