A 2.2-GHz 3.2-mW DTC-Free Sampling $\Delta\Sigma$  Fractional-$N$  PLL With −110-dBc/Hz In-Band Phase Noise and −246-dB FoM and −83-dBc Reference Spur

Tao, Jingcheng; Heng, Chun-Huat

doi:10.1109/tcsi.2019.2926326

Cited by 16 publications

(10 citation statements)

References 20 publications

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“…It is observed from Table 4 that the proposed ADPLL has fast locking time as compared to designs in previous papers 17,23,24 . There is a reduction of 45% in the locking time and 11% reduction in the power consumption with expense of only 7% increase in the jitter as compared to architecture reported in Sahani et al 17 The proposed ADPLL has better jitter and power consumption as compared to work presented in the Tao and Heng 22 . The locking time is 1.7 μs of proposed ADPLL after postlayout simulations.…”

Section: Discussionmentioning

confidence: 68%

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator

Sahani

Singh

Agarwal

2022

Circuit Theory & Apps

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A dual‐loop ADPLL architecture with 3‐bit flash TDC and background calibration‐based VCO is presented in this paper. The major aim of this work is to achieve the low jitter, low power, fast locking, and PVT‐insensitive ADPLL using simple flash TDC and gain calibrated VCO. A simple flash‐based 3‐bit TDC in the main loop is used which helps in achieving the fast locking with lower power consumption in ADPLL. The novel low phase noise VCO, with gain calibration in another loop, is used to fasten the locking process and jitter reduction due to any PVT variations. Therefore, both flash TDC and dual loop in the proposed ADPLL architecture help in achieving the fast locking. Proposed ADPLL is designed in SCL 180 nm CMOS technology at 1.8 V. The resolution of 3‐bit flash TDC is 3 ps. The achieved jitter of ADPLL is 1.83 ps with a phase noise of −153 dBc/Hz and locking time of 1.7 μs. Total power consumption is 5.3 mW at a frequency of 1.6 GHz.

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Section: Discussionmentioning

confidence: 68%

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator

Sahani

Singh

Agarwal

2022

Circuit Theory & Apps

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“…For other noises, PI resolution in our design is equal to 1/32 times 2T VCO . Based on this, quantitative analysis shows that the proposed design has 24 dB lower quantization noise compared to the conventional fractional-N divider [20]. Overall, the sum of in-band noise sources except for VCO (which will be explained in the succeeding paragraph) has been found to be −134 dBc/Hz, which is sufficient performance for most targeted applications.…”

Section: Noise Analysismentioning

confidence: 75%

“…Here, PI adds various delays to the VCO output signal, so that the frequency of the FDB_PI signal changes over time. Furthermore, after PI units, [20] uses Linear Slope Generator (LSG) to linearize the sampling region. The LSG tilts the slope of the incoming signal from the PI to provide a wider linear region to sample with the REF_D signal.…”

Section: Sub-sampling Pll and Reference-sampling Pllmentioning

confidence: 99%

“…This 5-phase signal is interpolated into 32 phases through a consecutive 3-bit pipelined PI. Among 32 phase signals, only 3 adjacent signals are selected through DSM code [20] and sent to the following PSCG unit. The PSCG device then creates a sampling window that adaptively changes the activation time so that only the required VCO output pulses pass selectively as the sampling pulses.…”

Section: Architecture Overviewmentioning

confidence: 99%

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A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator

Han

Eom

Choi

et al. 2021

Sensors

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Sampling-based PLLs have become a new research trend due to the possibility of removing the frequency divider (FDIV) from the feedback path, where the FDIV increases the contribution of in-band noise by the factor of dividing ratio square (N2). Between two possible sampling methods, sub-sampling and reference-sampling, the latter provides a relatively wide locking range, as the slower input reference signal is sampled with the faster VCO output signal. However, removal of FDIV makes the PLL not feasible to implement fractional-N operation based on varying divider ratios through random sequence generators, such as a Delta-Sigma-Modulator (DSM). To address the above design challenges, we propose a reference-sampling-based calibration-free fractional-N PLL (RSFPLL) with a phase-interpolator-linked sampling clock generator (PSCG). The proposed RSFPLL achieves fractional-N operations through phase-interpolator (PI)-based multi-phase generation instead of a typical frequency divider or digital-to-time converter (DTC). In addition, to alleviate the power burden arising from VCO-rated sampling, a flexible mask window generation method has been used that only passes a few sampling clocks near the point of interest. The prototype PLL system is designed with a 65 nm CMOS process with a chip size of 0.42 mm2. It achieves 322 fs rms jitter, −240.7 dB figure-of-merit (FoM), and −44.06 dBc fractional spurs with 8.17 mW power consumption.

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“…5(b)-(d). During the first step φ chrg , the current source in the slope generator, I SG , charges the load capacitor, C SG , between the falling edges of REF and DIV [41], [42], converting its input time difference into a corresponding voltage…”

Section: A Phase Detector 1) Operating Principlementioning

confidence: 99%

A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <−54-dBc Spurs Under 50-mVpp Supply Ripple

Chen

Gong

Staszewski

et al. 2022

IEEE J. Solid-State Circuits

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In this article, we present a 4.5-5.1-GHz fractional-N digitally intensive phase-locked loop (DPLL) capable of maintaining its performance in face of a large supply ripple, thus enabling a direct connection to a switched-mode dc-dc converter. Supply pushing of its inductor-capacitor (LC) oscillator is suppressed by properly replicating the supply ripple onto the gate of its tail current transistor, while the optimum replication gain is determined by a new on-chip calibration loop tolerant of supply variations. A proposed configuration of cascading a supply-insensitive slope generator with an output of a current digital-to-analog converter (DAC) linearly converts the phase error timing into a corresponding voltage, which is then quantized by a successive approximation register (SAR) analog-to-digital converter (ADC) to generate a digital phase error. We also introduce a low-power ripple pattern estimation and cancellation algorithm to remove the phase error component due to the supply-induced delay variations of loop components. Implemented in 40-nm CMOS, the DPLL prototype achieves the performance of 428-fs rms jitter, <−55-dBc fractional spur, and <−54-dBc maximum spur while consuming 3.25 mW and being subjugated to a sinusoidal or sawtooth supply ripple of 50 mV pp at 50-MHz reference divided by 3, 6, or 12.

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A 2.2-GHz 3.2-mW DTC-Free Sampling $\Delta\Sigma$ Fractional-$N$ PLL With −110-dBc/Hz In-Band Phase Noise and −246-dB FoM and −83-dBc Reference Spur

Cited by 16 publications

References 20 publications

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator

A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator

A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <−54-dBc Spurs Under 50-mVpp Supply Ripple

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