A 2.18-pJ/conversion, 1656-μm² Temperature Sensor With a 0.61-pJ·K² FoM and 52-pW Stand-By Power

Abstract

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A Digital Improvement—Trimming a Digital Temperature Sensor with EEPROM Reprogrammable Fuses

“…The performances of the trimmed thermal sensor ( Figure 3 ) are compared with recently reported digital temperature sensors [ 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 ] in Table 2 . The experimental results of 25 measured DTS samples are in good agreement with the majority of referred data [ 4 , 5 , 6 , 11 , 12 , 13 , 14 , 15 , 18 , 19 , 21 , 24 ], providing low inaccuracy in a wide temperature range. Furthermore, the proposed trimmed DTS can be supplied with an extended domain of supply voltages.…”

“…Furthermore, the proposed trimmed DTS can be supplied with an extended domain of supply voltages. The presented digital sensor achieves its performance by calibration to just one point, while the inaccuracies obtained in [ 7 , 8 , 9 , 11 , 13 , 18 , 20 , 21 , 22 , 24 ] are performed using the two-point calibration method. With regards to power consumption, the investigated sensor reaches an acceptable value in comparison with [ 11 , 12 , 18 , 22 ].…”

“…Modern CMOS smart temperature sensors are categorized according to the sensing device (BJT, MOS in subthreshold region and resistor) or the physical principle on which the temperature is detected (bandgap voltage and thermal diffusion (TD)) [ 7 , 8 ]. Increased accuracy, high precision, and output linearity with low power consumption are some of the most important targets to achieve when designing such integrated sensors [ 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 ]. The aim to meet these requirements with low production costs becomes more and more challenging these days.…”

A Compact Fully Dynamic Capacitance-to-Digital Converter With Energy-Efficient Charge Reuse

“…4(a)], an ADC comparator with pMOS input transistors is used. Furthermore, the SAR ADC (except for the memory cells) is automatically power gated [5] after the conversion is finished (Fig. 3) to minimize the leakage power of the CDC.…”

“…Moreover, a compact SAR ADC with unit-length digital-to-analog (DAC) capacitors [4] is used to reduce the number of capacitors and the value of the unit capacitor. Furthermore, an automatic power-gating technique [5] is exploited to minimize the leakage power of the all-dynamic CDC. This letter is an extended version of [6], and it is organized as follows: the proposed CDC is introduced in Section II, the measurement results are presented in Section III, and conclusions are drawn in Section IV.…”