A 180-mV subthreshold FFT processor using a minimum energy design methodology

Abstract. Subthreshold design has been proposed as an effective technique for designing signal processing circuits needed in wireless sensor nodes powered by sources with limited energy. In this paper we propose a subthreshold FIR architecture which brings the benefits of reduced leakage energy, reduced minimum energy point, reduced operating voltage and increased operating frequency when compared with recently reported subthreshold designs. We shall demonstrate this through the design of a 9-tap FIR filter operating at 220mV with operational frequency of 126kHz/sample consuming 168.3nW or 1.33pJoules/sample. Furthermore, the area overhead of the proposed method is less than that of the transverse structure often employed in subthreshold filter designs. For example, a 9-tap filter based on transverse structure has 5× higher area than the filter designed using our proposed method.

Section: Introduction and Related Workmentioning

confidence: 99%

Subthreshold FIR Filter Architecture for Ultra Low Power Applications

Mishra

Al-Hashimi

2009

“…The custom variable-length Lin [7] FFT-processor employs radix-2/4/8 single-path delay algorithm. MIT FFT uses subtreshold circuit techniques [8].…”

Section: Performance Analysismentioning

confidence: 99%

Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform

Pitkänen

Makinen

Heikkinen

et al. 2006

Abstract. Transport Triggered Architecture (TTA) offers a cost-effective tradeoff between the size and performance of ASICs and the programmability of general-purpose processors. This paper presents a study where a high performance, low power TTA processor was customized for a 1024-point complexvalued fast Fourier transform (FFT). The proposed processor consumes only 1.55 µJ of energy for a 1024-point FFT. Compared to other reported FFT implementations with reasonable performance, the proposed design shows a significant improvement in energy-efficiency.

“…Several successful implementations of digital circuits operating in the subthreshold regime are available in the literature [6,10]. Circuits operating at these extreme low supply voltages work at much lower speeds, i. e., the FFT processor presented in [10] has a maximum clock frequency of 10 kHz with a power supply of 350 mV.…”

Section: Introductionmentioning

confidence: 99%

Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-V t Domain By Architectural Folding

Rodrigues

Akgun

Acharya

et al. 2010

Abstract. This manuscript presents the digital hardware realization of a wavelet based event detector for cardiac pacemaker applications. The architecture of the detector is partially folded to minimize hardware cost. An energy model is applied to evaluate the energy efficiency in the sub-threshold (sub-VT ) domain. The design is synthesized in 65 nm low leakage-high threshold CMOS technology, and it is shown that folding reduces the area cost by 30.6 %. Due to folding, energy efficiency of the circuit is increased by 14.4 % in the sub-VT regime, where the circuit dissipates 3.3 pJ per sample at VDD=0.26 V.