A 170 volt polysilicon-emitter complementary bipolar IC technology with full dielectric isolation

McGregor, J.M.; Yindeepol, W.; DeSaints, J.; Brown, Kevin C.; Bashir, Rashid; McKeown, W.

doi:10.1109/bipol.1997.647431

Cited by 4 publications

(6 citation statements)

References 3 publications

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“…The detailed bipolar process flow is described elsewhere [4]. In summary, N /P buried layers were implanted, and driven for the BJT 16 -cm, N-type epitaxial layer was grown to a thickness necessary for the achieving the required breakdown voltages.…”

Section: Process Flow and Electrical Resultsmentioning

confidence: 99%

“…There has been rapid progress in BESOI manufacturing technology and a variety of substrates are now commercially available. The use of BESOI substrates to provide device isolation for a 170 V dielectrically isolated complementary bipolar technology has been recently reported [4]. While deep trenches provide lateral isolation, the use of SOI provides vertical device isolation for high voltages, eliminating the need for deep wells used in previous technologies [5].…”

mentioning

confidence: 99%

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Back-gated buried oxide MOSFETs in a high-voltage bipolar technology for bonded oxide/SOI interface characterization

Bashir

Wang

Greig

et al. 1998

IEEE Electron Device Lett.

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Abstract-A novel back-gated P-MOSFET structure is fabricated in a high-voltage complementary bipolar technology using BESOI (bonded etch back SOI) substrates. The P+ buried layer regions, used for the PNP BJT are used as the source and drain regions, the N-epi as the channel region, the silicon handle wafer as the gate, and the BOX (buried oxide) as the gate oxide. The P-MOSFET was used to characterize the interface between the BOX and the SOI. The devices exhibit high sub-threshold slope which is attributed to a high interface state density of about 2210 12 #=cm 2 at the bonding interface. Bias-temperature stress measurements show an effective mobile charge density of 4 2 10 10 #=cm 2 in the buried oxide.

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Section: Process Flow and Electrical Resultsmentioning

confidence: 99%

mentioning

confidence: 99%

Back-gated buried oxide MOSFETs in a high-voltage bipolar technology for bonded oxide/SOI interface characterization

Bashir

Wang

Greig

et al. 1998

IEEE Electron Device Lett.

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“…In order to reduce parasitics, various authors have reported devices fabricated on silicon-on-insulator (SOI) wafers and trench isolation. Bonded and etched back SOI (BESOI) wafers have found significant use in these processes [15], [18]- [21], [26], [35]- [37]. SOI wafers make the process simpler, i.e., no n-wells are needed for the PNP device isolation, and the device size and parasitic capacitances are reduced.…”

Section: Review Of Complementary Bipolar Technologiesmentioning

confidence: 99%

“…In order to fulfill the need for high-precision and high-frequency analog circuits, a family of complementary silicon bipolar processes has been developed [29], [30], [35], [36]. Three technologies named VIP-3, VIP-3H, and VIP-4H are described in the following.…”

Section: Vip™ Process Detailsmentioning

confidence: 99%

“…For the VIP-4H process, a magnetically enhanced reactive ion etch system (MERIE) was used to define the deep trenches utilizing an HBr/NF /He-O plasma chemistry [31], [35], [36], [55], [56]. The primary benefit of an azimuthally rotating magnetic field parallel to the wafer surface is enhancement of ionization rate by induction of electrons into helical trajectories between collisions allowing lower pressure operation without loss of etch rate [57].…”

Section: Trench Isolation and Characterizationmentioning

confidence: 99%

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A complementary bipolar technology family with a Vertically Integrated PNP for high-frequency analog applications

Bashir

Hebert²,

DeSantis³

et al. 2001

IEEE Trans. Electron Devices

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Abstract-Silicon complementary bipolar processes offer the possibility of realizing high-performance circuits for a variety of analog applications. This paper presents a summary of silicon complementary bipolar process technology reported in recent years. Specifically, an overview of a family of silicon complementary bipolar process technologies, called Vertically Integrated PNP (VIP™ 1 ), which have been used for the realization of high-frequency analog circuits is presented. Three process technologies, termed VIP-3, VIP-3H, and VIP-4H offer device breakdowns of 40, 85, and 170 V, respectively. These processes feature optimized vertically integrated bipolar junction transistors (PNPs) along with high performance NPN transistors with polycrystalline silicon emitters, low parasitic polycrystalline silicon resistors, and metal-insulator-polycrystalline silicon capacitors. Key issues and aspects of the processes are described. These issues include the polycrystalline silicon emitter optimization and vertical and lateral device isolation in the transistors. Circuit design examples are also described which have been implemented in these technologies.

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Modeling and characterization of deep trench isolation structures

Lee¹,

Bashir²

2001

Microelectronics Journal

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In this paper, we present a simple equivalent electrical circuit model and sidewall interface characterization results for a deep trench isolation structure. The trench structures used in the study consisted of n-silicon/undoped trench/n-silicon. The trenches were ®lled with undoped polycrystalline silicon and the trench sidewall was lined with thermal oxide and a deposited silicon nitride. The capacitance±voltage characteristics across the trench were measured and compared against the model predictions. The circuit model includes the effect of the space-charge region and recombination±generation currents in the undoped polycrystalline silicon trench ®ll material. The Terman method was used to extract the silicon/oxide sidewall interface density and the mid gap value was found to be less than 10 210 #/cm 2 -eV. q

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A 170 volt polysilicon-emitter complementary bipolar IC technology with full dielectric isolation

Cited by 4 publications

References 3 publications

Back-gated buried oxide MOSFETs in a high-voltage bipolar technology for bonded oxide/SOI interface characterization

Back-gated buried oxide MOSFETs in a high-voltage bipolar technology for bonded oxide/SOI interface characterization

A complementary bipolar technology family with a Vertically Integrated PNP for high-frequency analog applications

Modeling and characterization of deep trench isolation structures

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