A 16nm FinFET CMOS Technology for Mobile SoC and Computing Applications

Wu, Shuo‐Jye; Lin, Chunn-Yenn; Chiang, Meng-Hsueh; Liaw, J.J.; Cheng, Jerry; Yang, Shanglin; Yao, C.H.; Lee, T.L.; Chang, Weichun; Chen, C.C.; Tsai, Ming-Feng; Jang, Seunghyun; Chen, K.S.; Ku, Yun Hyi

doi:10.7567/ssdm.2014.j-3-1

Cited by 25 publications

(20 citation statements)

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“…For example, at 14nm GlobalFoundries has stated that it uses a fin pitch of 48nm and a metal pitch of 64nm [7]. The same values are used in TSMC's 16nm process [5]. In addition, not all fin tracks are available for active transistors.…”

Section: Track Heightmentioning

confidence: 97%

“…In addition, the amount of doping feasible in a fin is also limited, which restricts the number of available device Vt options (e.g. to 3 in TSMC 16nm [5]). …”

Section: Introductionmentioning

confidence: 99%

“…Manufacturing issues limit the options available in gate lengths. For example, TSMC's 16nm process allows for 3 discrete gate lengths: 30nm, 34nm, and 50nm [5]. In addition, the amount of doping feasible in a fin is also limited, which restricts the number of available device Vt options (e.g.…”

Section: Introductionmentioning

confidence: 99%

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Physical design and FinFETs

Aitken

Yeric

Cline

et al. 2014

Proceedings of the 2014 on International Symposium on Physical Design

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Section: Track Heightmentioning

confidence: 97%

“…In addition, the amount of doping feasible in a fin is also limited, which restricts the number of available device Vt options (e.g. to 3 in TSMC 16nm [5]). …”

Section: Introductionmentioning

confidence: 99%

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Physical design and FinFETs

Aitken

Yeric

Cline

et al. 2014

Proceedings of the 2014 on International Symposium on Physical Design

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“…It is therefore important to reduce the noise of FinFET for the application to those circuits. The noise characteristics of FinFET have been reported in some technical journals and conferences [12]- [15]. We focus on fin width dependence of the noise and analyze the dependence by using our simulator for the first time.…”

Section: Analog Performancementioning

confidence: 99%

Technology of FinFET for High RF and Analog/Mixed-Signal Performance Circuits

Ohguro

Inaba

Kaneko

et al. 2015

IEICE Trans. Electron.

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SUMMARY In this paper, we discuss the process, layout and device technologies of FinFET to obtain high RF and analog/mixed-signal performance circuits. The fin patterning due to Side-wall transfer (SWT) technique is useful to not only fabricate narrow fin line but also suppress the fin width variation comparing with ArF and EB lithography. The H 2 annealing after Si etching is useful for not only to improve the mobility of electron and hole but also to reduce flicker noise of FinFET. The noise decreases as the scaling of fin width and that of FinFET with below 50 nm fin width is satisfied with the requirement from 25 nm technology node in ITRS roadmap 2013. This lower noise is attributed to the decrease of electric field from the channel to the gate electrode. Additionally, the optimum layout of FinFET is discussed for RF performance. In order to obtain higher f T and f max , it is necessary to have the optimized finger length and reduced capacitances between the gate and Si substrate and between gate and source, drain contact region. According to our estimation, the f T of FinFET with the optimized layout should be lower than that of planar MOSFET when the gate length is longer than 10 nm due to larger gate capacitance. In conclusion, FinFET is suitable for high performance digital and analog/mixed-signal circuits. On the other hand, planar MOSFET is better rather than FinFET for RF circuits.

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“…Since the introduction of finFET technology at the 22nm node 72 , continuous reductions in the dimensions of the transistors have managed to maintain the aggressive pace of scaling as dictated by Moore's law 73,74,75 . Table 3 shows the target dimensions from the 22nm to the 7nm node, and Fig.…”

Section: Feol Integration Challenges In Developing Non-planar Finfet mentioning

confidence: 99%

Scaling Challenges for Advanced CMOS Devices

Jacob

Xie

Sung

et al. 2017

Int. J. Hi. Spe. Ele. Syst.

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The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore's law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

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A 16nm FinFET CMOS Technology for Mobile SoC and Computing Applications

Cited by 25 publications

References 0 publications

Physical design and FinFETs

Physical design and FinFETs

Technology of FinFET for High RF and Analog/Mixed-Signal Performance Circuits

Scaling Challenges for Advanced CMOS Devices

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