A 16mb Dram with an Open Bit-Line Architecture

Abstract

THIS PAPER WILL COVER A 16Mb DRAM with a 6511s RAS access time and 5.4mm x 17.38mm (93.85mm2) chip in a 300mil dual-in-line package. The chip was fabricated in 0 . 5~ N-well CMOS technology with double-poly, single-polycide and double-metal. To package a 16Mb DRAM in a 300mil DIP, the memory cell size has t o be less than 4pm2 maintaining a capacitance large enough for alpha-particle-induced soft error tolerance and the stable operation. Open bit-line architecture can provide a small geometry memory cell, resulting in a high density cell array'. However, in conventional open bit-line architectures, total packing density of 16Mb DRAM cannot be improved, since the scaling of cell size is limited by the layout pitch of the sense amplifiers. To overcome this problem, we developed an open bit-line architecture based o n a double layer bit-line and a surrounding Hi-capacitance trench cell s t r n c t~r e ' '~'~. Figure 1 shows the circuit configuration of the relaxedsense-amplifier-pitch open bit-line architcture. Memory cells were arranged at all the cross points of word lines and segmented bit lines. The pitch of the sense amplifier is equal to double pitch of the segmented bit lines. The segmented bit lines are connected alternately to either side of the sense amplifiers. The sense amplifiers are connected t o two staggered segmented bit lines of adjacent segments. Further, two sense amplifiers were arranged in between a pair of global bit lines. A word-line selects four memory cells for every pair of global bit lines. In concurrence with the word-line selection, four sense amplifiers on both sides of the selected word-line are activated by SE. The complementary outputs of one of the four sense amplifiers are selectively connected to global bit lines via the segment-select switches controlled by column addresses. inferior to that of the folded bit-line architectures. This problem was solved b y adopting a reversal dummy word-line technique5. To date, the noise immunity of open bit-line architecture has been ' S h a h , A.H., e t al., "A 4Mb DRAM ., 1987. ' K o t a n i , H., e t al., "4Mb DRAM Design Including 1 6 b C o n c u r r e n t ECC", S y m p o s i u m o n V L S I Circuits Digest o f Technical Papers, p. 87-88; May, 1987. 4Fuse, G., e t al., "SCC(Surrounded Capacitor Cell) Strue ture for DRAM", E x t e n d e d A b s t r aOne reversal dummy word-line is arranged in each segment which has 256 word lines. Only a dummy word-line, which belongs to the segment lhaving an accessed word-line, goes t o low level. Other dummy word lines of non-selected segments are kept normally high level. Consequently, the noise that occurs by coupling between the word-line and the bit-line is canceled. Figures 2 and 3 show a physical layout and cross-sectionalviews of the memory cell. Minimum cell size can be achieved in the open bit-line architecture b y adopting the Surrounding Hi-Capacitance cell (SCC) structure. The storage capacitor is formed on the side-walls of the trench, which completely surrounds the hi-channel switching tr...

The DRAM Array

“…An alternative to the folded array architecture, popular prior to the 64kbit generation [1], was the open digitline architecture. Seen schematically in Figure 2.6, this architecture also features the sense amplifier circuits between two sets of arrays [8]. Unlike the folded array, however, true and complement digitlines (D and D*) connected to each sense amplifier pair come from separate arrays [9].…”

“…Again, two mbits share a common digitline contact to improve layout efficiency. Unfortunately, most manufacturers have found that the signal-to-noise problems of open digitline architecture outweigh the benefits derived from reduced array size [8].…”