A 160 Mpixel/s IDCT processor for HDTV

Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks

“…In addition, the SFG of LLM for forward and inverse DCTs are mirror images of one another and hence we can re-use the entire datapath for performing the forward and inverse transforms. As can be seen from Fig.1, for subsampled blocks of sizes 4x (1,2,4,8), we perform only the upper half computation(as indicated by the dashed line box) and for subsampled blocks of sizes 2x (1,2,4,8) we perform only the upper quarter computation(as indicated by the solid-line box). This is because the other coefficients are zero.…”

“…In the past, several architectures for DCT/IDCT processors for various application domains based on different algorithms have been proposed [12]. All the previous architectures have been optimised for either performing IDCT on fixed 8x8 blocks [1] typically used in decoders (MPEG, JPEG etc. ), or performing both FDCT and IDCT on fixed 8x8 blocks [2]- [6].…”

“…Paek et al [7] support a dual mode of operating on 8x8 blocks or 2x4x8 blocks for the digital VCR domain, thus providing support for scaled blocks of size 4x8. In our work, we go a step further by providing full support for scaled and sub-sampled blocks of sizes (1,2,4,8)x (1,2,4,8). Furthermore, the fixed point accuracy of our design meets the specifications of the CCITT [10] which is more stringent than that of the digital VCR domain.…”