A 160-MHz analog front-end IC for EPR-IV PRML magnetic storage read channels

Pai, Patrick; Brewster, Anthony; Abidi, A.A.

doi:10.1109/jssc.1996.542406

Cited by 50 publications

(5 citation statements)

References 41 publications

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“…The phase lag introduced by the parasitic pole may be compensated by placing a resistor in series with the integrating capacitor [16], [25], [26]. The resulting transfer function has two poles and a single zero (12) While this first-order passive compensation may be adequate in some implementations, it is evident from (12) that the parasitic pole and zero do not track each other because the transconductance of the cascode transistor varies with process, temperature, tuning etc. In practice, is a variable resistance implemented using a MOS transistor operating in the triode region whose gate is driven by some form of automatic phase-tuning circuitry [11].…”

Section: B Frequency Compensationmentioning

confidence: 99%

“…A slightly negative output conductance will not cause filter instability, however, because of negative feedback, loops inherently present in the biquadratic loop . Regardless, the most popular choice is the inclusion of a cascode stage (simple [9], [10], active [11], [12], folded [13], [14], telescopic [15], [16]) or a cascaded output stage such as the -op-amp [17]- [21] to improve the integrator dc gain, and attempt to cancel the associated parasitics directly.…”

Section: Introductionmentioning

confidence: 99%

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A Novel Pole–Zero Compensation Scheme Using Unbalanced Differential Pairs

Ryan

McCarthy

2004

IEEE Trans. Circuits Syst. I

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Abstract-The main problem in extending continuous-time filtering to higher frequencies is the sensitivity of high-frequency filters to analog integrator nonidealities such as finite dc gain and parasitic poles. The use of a cascode stage introduces internal nodes, and hence a nondominant pole, in the signal path. This has been overcome using a novel phase compensation scheme which does not require tuning of the compensating element, and is itself unaffected by tuning of the integrator's unity-gain frequency or quality factor. The scheme is based upon a MOS version of the "multi-tanh principle" where the linear range of a transconductor is divided between at least two unbalanced differential pairs operating in parallel. The common-source node of an unbalanced differential pair is not ac ground and the associated pole-zero pair may be harnessed to cancel the parasitic pole introduced by the cascode stage. The feasibility of the proposed design was evaluated with the fabrication of a test-chip on a 0.25 m 2.5 V standard digital CMOS process. Measurements confirm that the group delay response is flat ( 2%) over a five octave frequency range (3.5-112 MHz or 0.058-1.87 ).

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Section: B Frequency Compensationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Novel Pole–Zero Compensation Scheme Using Unbalanced Differential Pairs

Ryan

McCarthy

2004

IEEE Trans. Circuits Syst. I

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“…The linearity of the voltage-to-current transducer can be improved employing source degeneration techniques, as shown in Fig. 1(a) [2], [3], [5]- [8], [10], [12], [13]. The OTA small-signal transconductance is tuned by adjusting the gate voltage of transistor , which operates in triode region.…”

Section: Otamentioning

confidence: 99%

“…The small-signal transconductance of CMOS devices, unlike bipolar devices, increases with both current and gate dimensions, and usually for high-frequency applications the resulting circuits require high power consumption and huge transistor dimensions that increase the parasitic capacitors. The design is even more complex due to the additional circuitry used for the linearization of the OTA [1]- [3], [5]- [13] and tuning.…”

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confidence: 99%

A 60-mW 200-MHz continuous-time seventh-order linear phase filter with on-chip automatic tuning system

Silva-Martínez

Adut

Rocha-Pérez

et al. 2003

IEEE J. Solid-State Circuits

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A full CMOS seventh-order linear phase filter based on-biquads with a 3-dB frequency of 200 MHz is realized in 0.35-m CMOS process. The linear operational transconductance amplifier is based on complementary differential pairs in order to achieve both low-distortion figures and high-frequency operation. The common-mode feedback (CMFB) employed takes advantage of the filter architecture; incorporating the load capacitors into the CMFB loop improves further its phase margin. A very simple automatic tuning system corrects the filter deviations due to process parameter tolerances and temperature variations. The group delay ripple is less than 5% for frequencies up to 300 MHz, while the power consumption is 60 mW. The third-harmonic distortion is less than 44 dB for input signals up to 500 mV pp. The filter active area is only 900 200 m 2. The supply voltages used are 1.5 V.

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“…This track-mode bandwidth of this circuit must exceed 1GHz, and at half-Nyquist input frequency its dynamic distortion must be below -40dBc. A passive FET switch connected to a sampling capacitor through a dummy switch fulfills these requirements [3]. The main sources of distortion are signaldependent charge injection on switch closure, nonlinearity of the input buffer, and dynamic current into the signal-dependent input capacitance of the comparator array.…”

mentioning

confidence: 99%

A 6 b 1.3 GSample/s A/D converter in 0.35 μm CMOS

Choi¹,

Abidi²

2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)

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Digital receivers for high bit-rate communications are spurring on the required conversion rate of A/D converters. State-of-theart disk drive read channels and high-speed Ethernet signals use partial response signaling, requiring 6b resolution at conversion rates of 1GHz and beyond, and an effective resolution bandwidth of half the Nyquist frequency. Furthermore, continuous DVD playback and certain Ethernet uses permit no idle times when the linearity of the A/D converter may be self-calibrated by autozeroing. This work reports on a 6b ADC without autozero or selfcalibration, which digitizes a 630MHz input with a linearity of 5.5 effective bits at 1GSample/s, and a 650MHz input with 5 effective bits at 1.3GSample/s. At conversion rates of 1GSample/s and beyond, the only practical architecture to date is the flash ADC. As MOSFETs in the preamplifiers are sized up to lower random mismatch to resolve a typical full-scale of 1.6V to 6b, the power consumption and input capacitance also grow to a point that the ADC may no longer be readily embedded in a receiver chip. This ADC uses resistor averaging in two places to filter out random mismatch between arrays of differential pairs, substantially improving the accuracy of small MOSFETs which bias at a small current and present low input capacitance. Previous work [1] presents a systematic method to design averaging networks based on spatial filtering. With the proper number of dummy preamplifiers at each end of the array, the optimum averaging network lowers INL by 3.3x. To obtain the same linearity without averaging, FET W/L, and therefore power dissipation, must be scaled by 10x.

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A 160-MHz analog front-end IC for EPR-IV PRML magnetic storage read channels

Cited by 50 publications

References 41 publications

A Novel Pole–Zero Compensation Scheme Using Unbalanced Differential Pairs

A Novel Pole–Zero Compensation Scheme Using Unbalanced Differential Pairs

A 60-mW 200-MHz continuous-time seventh-order linear phase filter with on-chip automatic tuning system

A 6 b 1.3 GSample/s A/D converter in 0.35 μm CMOS

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