A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network

Taylor, Michael; Kim, J.; Miller, Joel B.; Wentzlaff, David; Ghodrat, F.; Greenwald, Bruce C.; Hoffman, Henry; Johnson, Paul R.; Lee, W.; Saraf, Arvind; Shnidman, Nathan; Strumpen, Volker; Amarasinghe, Saman; Agarwal, Anant

doi:10.1109/isscc.2003.1234253

Cited by 50 publications

(25 citation statements)

References 2 publications

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“…The low complexity 2D mesh has been used by most fabricated many-core systems including RAW [5], AsAP [6], TILE64 [7], AsAP2 [8] and Intel 48-core Single-Chip Cloud Computer (SCC) [9].…”

Section: Related Workmentioning

confidence: 99%

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

Xiao

Baas

2013

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design

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Abstract. Network-on-Chips (NoCs) are used to connect large numbers of processors in many-core processor architecture because they perform better than less scalable methods such as global shared buses. Among all NoC design parameters, NoC topologies define how nodes are placed and connected and greatly affect the performance, energy efficiency, and circuit area of many-core processor arrays. Due to its simplicity and the fact that processor tiles are traditionally square or rectangular, 2D mesh is mostly used for existing on-chip networks. However, efficiently mapping applications can be a challenge for cases that require communication between processors that are not adjacent on the 2D mesh. Motivated by the fact that applications often have largely localized communication patterns, we have proposed an 8-neighbor mesh topology and a 6-neighbor topology with hexagonal-shaped processor tiles, both of which increase local connectivity while keep much of the simplicity of a mesh-based topology. We have physically designed a 16-bit DSP processor and the corresponding processor arrays which utilize all three topologies. A 1080p H.264/AVC residual video encoder and a 54 Mbps 802.11a/11g OFDM wireless LAN baseband receiver are mapped onto all topologies. The 6-neighbor hexagonal grid topology incurs a 2.9% area increase per tile compared to the 4-neighbor 2D mesh, but its much more effective interprocessor interconnect yields an average total application area reduction of 21%, an average power reduction of 17%, and a total application interprocessor communication distance reduction of 19%.

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“…The low complexity 2D mesh has been used by most fabricated many-core systems including RAW [5], AsAP [6], TILE64 [7], AsAP2 [8] and Intel 48-core Single-Chip Cloud Computer (SCC) [9].…”

Section: Related Workmentioning

confidence: 99%

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

Xiao

Baas

2013

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design

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“…Even with the control overheads of vector-threading and its nonblocking cache, Scale's 16 execution clusters provide relatively dense computation. The core area is around the same size as a single tile in the 16-tile RAW microprocessor [Taylor et al 2003]. In 130 nm technology, around 40 Scale cores could fit within the area of the twocore TRIPS processor [Sankaralingam et al 2006].…”

Section: Areamentioning

confidence: 99%

Implementing the scale vector-thread processor

Krashinsky

Batten

Asanović

2008

ACM Trans. Des. Autom. Electron. Syst.

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The Scale vector-thread processor is a complexity-effective solution for embedded computing which flexibly supports both vector and highly multithreaded processing. The 7.1-million transistor chip has 16 decoupled execution clusters, vector load and store units, and a nonblocking 32KB cache. An automated and iterative design and verification flow enabled a performance-, power-, and areaefficient implementation with two person-years of development effort. Scale has a core area of 16.6 mm 2 in 180 nm technology, and it consumes 400 mW-1.1 W while running at 260 MHz.

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“…To maintain link communication at full clock rates, inter-processor connections are made to nearestneighbor processors only. A number of architectures including wavefront [9], RAW [10], and TRIPS [11], have specifically addressed this concern and have demonstrated the advantages of a tile-based architecture. AsAP's nearest neighbor connections result in no high-speed wires with a length greater than the linear dimension of a processing element.…”

Section: Reconfigurable Two-dimensional Mesh Networkmentioning

confidence: 99%

“…A wide range of granularities are possible as shown in Fig. 6 [6,10,15,16]. The coarse grain two-core Itanium [16] contains large wide-issue processors each close to 300 mm 2 in 90 nm technology, while the fine grain AsAP contains single-issue processors less than 1 mm 2 in 0.18 μm technology.…”

Section: Analysis Of the Key Featuresmentioning

confidence: 99%

Architecture and Evaluation of an Asynchronous Array of Simple Processors

Meeuwsen

Apperson

et al. 2008

J Sign Process Syst Sign Image Video Technol

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This paper presents the architecture of an asynchronous array of simple processors (AsAP), and evaluates its key architectural features as well as its performance and energy efficiency. The AsAP processor calculates DSP applications with high energyefficiency, is capable of high-performance, is easily scalable, and is well-suited to future fabrication technologies. It is composed of a two-dimensional array of simple single-issue programmable processors interconnected by a reconfigurable mesh network. Processors are designed to capture the kernels of many DSP algorithms with very little additional overhead. Each processor contains its own tunable and haltable clock oscillator, and processors operate completely asynchronously with respect to each other in a globally asynchronous locally synchronous (GALS) fashion. A 6 × 6 AsAP array has been designed and fabricated in a 0.18 μm CMOS technology. Each processor occupies 0.66 mm 2 , is fully functional at a clock rate of 520-540 MHz at 1.8 V, and dissipates an average of 35 mW per processor at 520 MHz under typical conditions while executing applications such as a JPEG encoder core and a complete IEEE 802.11a/g wireless LAN baseband transmitter. Most processors operate at over 600 MHz at 2.0 V. Processors dissipate 2.4 mW at 116 MHz and 0.9 V. A single AsAP processor occupies 4% or less area than a single processing element in other multi-processor chips. Compared to several RISC processors (single issue MIPS and ARM), AsAP achieves performance 27-275 times greater, energy efficiency 96-215 times greater, while using far less area. Compared to the TI C62x high-end DSP processor, AsAP achieves performance 0.8-9.6 times greater, energy efficiency 10-75 times greater, with an area 7-19 times smaller. Compared to ASIC implementations, AsAP achieves performance within a factor of 2-5, energy efficiency within a factor of 3-50, with area within a factor of 2.5-3. These data are for varying numbers of AsAP processors per benchmark.

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A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network

Cited by 50 publications

References 2 publications

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

Implementing the scale vector-thread processor

Architecture and Evaluation of an Asynchronous Array of Simple Processors

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