Implementing the scale vector-thread processor

Abstract

The Scale vector-thread processor is a complexity-effective solution for embedded computing which flexibly supports both vector and highly multithreaded processing. The 7.1-million transistor chip has 16 decoupled execution clusters, vector load and store units, and a nonblocking 32KB cache. An automated and iterative design and verification flow enabled a performance-, power-, and areaefficient implementation with two person-years of development effort. Scale has a core area of 16.6 mm 2 in 180 nm technology, and it consumes 400 mW-1.1 W while running at 260 MHz.

Field-Programmable Gate Array (FPGA) Emulation for Computer Architecture

“…Given the multicore revolution, we claim that the biggest architectural research challenges now deal with multiple processors rather than increasingly sophisticated single processors. Indeed, there is even a commercial movement towards "manycore" architectures that use many simpler processors, such as the IBM Cell, Intel Larrabee, and Sun Niagara [21], [40], [26]. Hence, architecture investigations now need to be able to look at many processors in addition to memory hierarchy and processor design.…”