A 16-bit monolithic I<sup>3</sup>L processor

This paper describes methods of designing large Arithmetic and Logical Units (ALUs) using multiple Programmable Logic Array (PLA) macros in which the outputs are obtained in one cycle corresponding to one pass through any PLA. The design is based on the well-known technique of providing conditional sums and group carries in parallel and selecting the proper sum using gating circuits. The PLA for each group of hits uses an adder design published by Weinberger in which each bit of the sum is formed from the EXCLUSIVEOR of two outputs of the OR array. By placing the gating circuits in front of the EXCLUSIVE-OR circuits, the sums can be obtained using two OR array outputs for each bit and one additional OR array output for each internal string of bits. Also discussed are how ALUs containing more than two groups can obtain the group carries using a separate carry-look-ahead PLA macro cind how this macro can be compressed by using special decoders and special physical design layout techniques. Additionally, the paper demonstrates how the PLAs can he used to provide detection of overflow and of zero results, and to also provide Boolean operations.

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A 16-bit monolithic I³L processor

Cited by 3 publications

References 1 publication

Subnanosecond Self-Aligned I/sup 2/L/MTL Circuits

Subnanosecond Self-Aligned I/sup 2/L/MTL Circuits

Subnanosecond self-aligned I²L/MTL circuits

Design of Large ALUs Using Multiple PLA Macros

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A 16-bit monolithic I3L processor

Cited by 3 publications

References 1 publication

Subnanosecond Self-Aligned I/sup 2/L/MTL Circuits

Subnanosecond Self-Aligned I/sup 2/L/MTL Circuits

Subnanosecond self-aligned I2L/MTL circuits

Design of Large ALUs Using Multiple PLA Macros

Contact Info

Product

Resources

About

A 16-bit monolithic I³L processor

Subnanosecond self-aligned I²L/MTL circuits