A 16-bit CMOS Digitally Controlled Oscillator Using a Novel Control Scheme

Hasan, S. M. Rezaul; Ula, N.

doi:10.1109/mwscas.2006.382154

Cited by 4 publications

(3 citation statements)

References 6 publications

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“…The load capacitance can be changed by using MIM capacitor or MOS transistor at the output node of inverter. But it cannot be much useful in sub-micron technology as wired capacitance have significant portion in load capacitance, which in turn, limits the maximum oscillating frequency [6] of an oscillator. Thus, this approach would not be much useful to achieve wide turning range of an oscillator.…”

Section: Design Of Conventional Ring Oscil-latormentioning

confidence: 99%

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Design of Highly Linear, 1GHz 8-bit Digitally Controlled Ring Oscillator with Wide Tuning Range in 0.18um CMOS Process

Pokharel

Tomar

Kanaya

et al. 2008

2008 China-Japan Joint Microwave Conference

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This paper presents a simple architecture for 8-bit digital controlled oscillator (DCO) on 3-stages ring topology in TSMC 0.18um CMOS technology. A new schematic of tristate inverter is also proposed. The proposed tristate inverter has higher switching speed and low power consumption as compared to conventional one. The control digit changes the driving current that provides large tuning range from 316 MHz to 1165 MHz with very good linearity. The output voltage swing is always greater than 1.6V while the supply voltage is 1.8V. The proposed DCO has simulated phase noise of-114dBc/Hz @1MHz and 23.2mW power consumption at 1.0 GHz central frequency.

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Section: Design Of Conventional Ring Oscil-latormentioning

confidence: 99%

“…In Ref. [6], parallel resistors were used in transmission gate and control the resistance by changing digital control. It provides high load resistances means more power dissipation.…”

Section: Introductionmentioning

confidence: 99%

Design of Highly Linear, 1GHz 8-bit Digitally Controlled Ring Oscillator with Wide Tuning Range in 0.18um CMOS Process

Pokharel

Tomar

Kanaya

et al. 2008

2008 China-Japan Joint Microwave Conference

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“…2(a) is based on an inverter array with row and column digital inputs [1]- [2], and Fig. 2(b) shows the DAC based DCRO [3]- [4]. Since the digital control input directly modulates the DCRO in Fig.…”

Section: Introductionmentioning

confidence: 99%

A latency-proof quantization noise reduction method for digitally-controlled ring oscillators

Liu

Rui

Xiang

et al. 2010

2010 53rd IEEE International Midwest Symposium on Circuits and Systems

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This paper describes a quantization noise reduction method for ΔΣ based digitally-controlled ring oscillators (DCRO). A concept of the hybrid finite-impulse response (FIR) filter from the fractional-N PLL is extended to the DCRO design. Thanks to the parallel operation, the proposed filter based noise reduction method does not cause any additional latency to the digital PLL. Both behavioral and circuit-level simulations are performed, showing that out-of-band phase noise or short-term jitter caused by the ΔΣ modulator can be significantly reduced with the proposed method.

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Design of 1.1 GHz Highly Linear Digitally-Controlled Ring Oscillator with Wide Tuning Range

Tomar¹,

Pokharel²,

Nizhnik³

et al. 2007

2007 IEEE International Workshop on Radio-Frequency Integration Technology

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A 16-bit CMOS Digitally Controlled Oscillator Using a Novel Control Scheme

Cited by 4 publications

References 6 publications

Design of Highly Linear, 1GHz 8-bit Digitally Controlled Ring Oscillator with Wide Tuning Range in 0.18um CMOS Process

Design of Highly Linear, 1GHz 8-bit Digitally Controlled Ring Oscillator with Wide Tuning Range in 0.18um CMOS Process

A latency-proof quantization noise reduction method for digitally-controlled ring oscillators

Design of 1.1 GHz Highly Linear Digitally-Controlled Ring Oscillator with Wide Tuning Range

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