Design of Highly Linear, 1GHz 8-bit Digitally Controlled Ring Oscillator with Wide Tuning Range in 0.18um CMOS Process

Pokharel, Ramesh K.; Tomar, Akash; Kanaya, Haruichi; Yoshida, Keiji

doi:10.1109/cjmw.2008.4772508

Cited by 5 publications

(1 citation statement)

References 8 publications

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“…In fact, the tuning range of the DCOs sets the limit on the accuracy and programmability of the proposed architecture ( Pokharel et al, 2008). The required tuning range for a certain number of applications should be available under all process corners.…”

Section: Digitally Controlled Oscillatormentioning

confidence: 99%

A programmable multi-step cyclic Vernier time-to-digital converter

Raymond¹,

Ghoneima²,

Ismail³

2013

IJCAD

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Abstract:A new architecture for a time-to-digital converter (TDC) is presented in this paper. The programmability feature of the new proposed architecture allows for the reusability of the design for various applications requiring different resolution, throughput, area and power constraints. One of the main motives behind this work (besides the programmability feature) is trying to resolve the inherent TDC design tradeoffs between resolution, throughput and complexity. The new TDC was implemented using the TSMC 65 nm technology. A detailed transistor level design along with the system level analysis is presented. For a reliable operation, a new auto calibration scheme is proposed that guarantees the successful operation of the system. Simulation results show the successful operation of the proposed TDC and its ability to auto calibrate itself for any process corner. As an example, for a resolution of 4 ps with an input range of 1 ns, the proposed TDC had a throughput of 45 MS/s while maintaining a DNL of 0.85 LSB and INL of 0.93 LSB.Keywords: time measurement; time-to-digital converters; TDC; data conversion; calibration systems.Reference to this paper should be made as follows: Raymond, M., Ghoneima, M. and Ismail, Y. (2013) 'A programmable multi-step cyclic Vernier time-to-digital converter', Int.

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Section: Digitally Controlled Oscillatormentioning

confidence: 99%

A programmable multi-step cyclic Vernier time-to-digital converter

Raymond¹,

Ghoneima²,

Ismail³

2013

IJCAD

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Design of a Low-Power Varactor-Based DCO Using NMOS Switching Network as a Digital Control Technique

Dabas,

Kumar

2024

Lecture Notes in Electrical Engineering

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A low power varactor based digitally controlled oscillator design in 180 nm CMOS technology

Dabas,

Kumar

2023

SN Appl. Sci.

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This paper reports two distinct architectures for digitally-controlled oscillators (DCOs) utilizing MOS varactor, designed in TSMC 180 nm CMOS technology. The first DCO design employs a CMOS inverter, while the second design features a Three-Transistors (3T) NAND gate as a delay stage inverter. Using these delay stages, three-bit, five-bit, and seven-bit controlled DCO circuits have been designed. For the inverter-based DCO circuit, the frequency spans from 4.844 to 2.708 GHz, 2.523 to 0.853 GHz, and 1.364 to 0.253 GHz, with a power consumption of 0.958 mW, 1.597 mW, and 2.236 mW for three-bit, five-bit, and seven-bit DCO variants, respectively. Further, the 3T-NAND gate-based DCO circuit exhibits oscillation frequencies ranging from 2.024 to 0.517 GHz, 0.867 to 0.131 GHz, and 0.341 to 0.033 GHz, with the resulting power consumption of 0.335 mW, 0.559 mW, and 0.782 mW. Equally significant, the proposed inverter-based DCO attains phase noise of − 102.61 dBc/Hz@1MHz, − 99.65 dBc/Hz@1MHz, and − 117.54 dBc/Hz@1MHz, accompanied by corresponding figures of merit (FoM) 174.94 dBc/Hz, 161.27 dBc/Hz, and 165.10 dBc/Hz for three-bit, five-bit, and seven-bit control words, respectively. For the 3T-NAND gate-based DCO, phase noise levels register at − 93.51 dBc/Hz@1MHz, − 113.07 dBc/Hz@1MHz, and − 106.96 dBc/Hz@1MHz, with FoM values of 160.23 dBc/Hz, 166.70 dBc/Hz, and 150.30 dBc/Hz for three-bit, five-bit, and seven-bit DCO variants, respectively. The comprehensive analysis of the proposed DCOs demonstrates the power supply variations, phase noise deviations, and frequency variations. The reported DCOs perform better with regard to output frequency range, power consumption, and overall FoM.

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Design of Highly Linear, 1GHz 8-bit Digitally Controlled Ring Oscillator with Wide Tuning Range in 0.18um CMOS Process

Cited by 5 publications

References 8 publications

A programmable multi-step cyclic Vernier time-to-digital converter

A programmable multi-step cyclic Vernier time-to-digital converter

Design of a Low-Power Varactor-Based DCO Using NMOS Switching Network as a Digital Control Technique

A low power varactor based digitally controlled oscillator design in 180 nm CMOS technology

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