This paper considers a high‐speed bipolar RAM with the integration density of 4 kb, as an example. The access time and the operational margin are examined by simulation and actual measurement in representing the effect of the timing difference between address input signals (called skew) on the characteristics of the memory.
First, it is shown that the access time increases by approximately 0.9 ns (17 percent) by the skew. This is due to the operation of the sense amplifier producing the differential output. As a result of the skew, the switching of the sensing current is delayed and the period is produced in which the differential sense outputs are kept at the same potential. This equipotential period lasts longer due to the skew than in the case without a skew, which produces a waveform distortion in the data output signal. This waveform distortion increases the access time. However, the increase is suppressed by optimizing the timing design of the internal circuit.
Next, the memory cell potential in the transient state is considered and the relation between the skew and the operational margin is examined. It is shown as a result that when a skew exists, the circuit experiences a special transient state which is not observed when there is no skew. It is shown that the operational margin in this state is determined by the particular memory, cell with a large variation in the forward voltage VF of Schottky Barrier Diode (SBD). It has been proven useful to reduce the variation of VF and to increase the SBD capacitance to reduce the dependency on the skew.
Finally, the relation between the two forementioned skew dependencies and the internal address latch function is discussed.