A 14bit Digitally Self-Calibrated Pipelined ADC with Adaptive Bias Optimization for Arbitrary Speeds up to 40MS/s

Matsui, Hirofumi; Ueda, Mitsuru; Daito, Mutsuo; Iizuka, Kunihiko

doi:10.1109/vlsic.2005.1469398

Cited by 14 publications

(2 citation statements)

References 5 publications

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“…The logic circuits for the calibration and the compensation are implemented in an FPGA. The digital gain calibration [7] is applied to the first eight pipelined stages, and the proposed digital distortion calibration is applied to the first stage only. Fig.…”

Section: Resultsmentioning

confidence: 99%

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A 14-bit 20-MS/s Pipelined ADC with Digital Distortion Calibration

Daito¹,

Matsui²,

Ueda³

et al. 2005

2005 IEEE Asian Solid-State Circuits Conference

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We present a 14-bit 20-MS/s pipelined analog-todigital converter (ADC) using a new digital distortion calibration technique. The calibration parameters are obtained using the same system as the conventional digital gain calibration. The ADC has been fabricated in a 0.18-µm CMOS process and consumes 33.7 mW at 2.8 V. With the calibration it achieves 15-dB improvement of the third-order nonlinearity. The measured SNDR and SFDR are 71.6 dB and 82.3 dB respectively.

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Section: Resultsmentioning

confidence: 99%

“…The obtained parameters are stored in the circuit and used to compensate the ADC output in the conversion mode. In this architecture, two extra (fourteenth and fifteenth) stages are necessary to calculate the calibration parameters with the required accuracy for 14-bit quantization [7].…”

Section: Pipelined Adc With Gain Calibrationmentioning

confidence: 99%

A 14-bit 20-MS/s Pipelined ADC with Digital Distortion Calibration

Daito¹,

Matsui²,

Ueda³

et al. 2005

2005 IEEE Asian Solid-State Circuits Conference

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An ultra low area asynchronous combo 4/8/12-bit/quaternary A/D converter based on integer division

Petrellis

Birbas

Kikidis

et al. 2010

Microelectronics Journal

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High-performance data converters: Trends, process technologies and design challenges

Maloberti

2008

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems

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High-performance electronic systems use more and more use high-performance data converters for improving and shaping the architecture and opening new application perspectives. The current and future trend depends on old and new factors that include global economy, technology evolution and marketing. All these elements are driving forces and create new challenges for the designer that answer the requests of new applications by exploiting the advantages and limiting the drawbacks due to the amazing growth of process technologies.

show abstract

A 14bit Digitally Self-Calibrated Pipelined ADC with Adaptive Bias Optimization for Arbitrary Speeds up to 40MS/s

Cited by 14 publications

References 5 publications

A 14-bit 20-MS/s Pipelined ADC with Digital Distortion Calibration

A 14-bit 20-MS/s Pipelined ADC with Digital Distortion Calibration

An ultra low area asynchronous combo 4/8/12-bit/quaternary A/D converter based on integer division

High-performance data converters: Trends, process technologies and design challenges

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