High-performance data converters: Trends, process technologies and design challenges

Maloberti, Franco

doi:10.1109/apccas.2008.4745948

Cited by 6 publications

(3 citation statements)

References 27 publications

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“…System architectures benefit increasingly from data converters that are key components needed to push as much as possible processing into the digital domain [2]. In this respect, the design of ADCs and DACs for high-end applications, where energy consumption, low-voltage, speed and effective resolution represent key aspects, is still dominated by experience and empirical skills.…”

Section: Architectural and Technical Challengesmentioning

confidence: 99%

Editorial: ADC Modelling, Testing and Data Converter Analysis and Design

2012

Measurement

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Section: Architectural and Technical Challengesmentioning

confidence: 99%

Editorial: ADC Modelling, Testing and Data Converter Analysis and Design

2012

Measurement

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“…Balancing the output impedance by using interleaved topology is another solution but it introduces other problems such as gain error and duty cycle error [59]. Another source of error which causes distortion in current-steering DACs is the mismatch of the saturation Organizations 7 current of a MOS transistor [52][53][54][55]60]. On the other hand, the capacitive DACs (SC DACs) have not drawn much attention except for few recent publications [61][62][63].…”

Section: Introductionmentioning

confidence: 99%

“…6.1. The SC DAC uses the 6-3-3 split-segmented SC arrays which have 6 most significant bits (MSBs) of thermometer codes, 6 least significant bits (LSBs) of binary-weighted ones with 2 attenuated capacitors in the middle for reducing capacitance spread [60]. The mux-based 6-63 thermometer decoder is used to convert 6 MSBs of the input to 63 unary bits since it is more suitable for high speed than the logic-based one [52].…”

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confidence: 99%

Efficient Integrated Circuits for Wideband Wireless Transceivers

Duong

2016

Linköping Studies in Science and Technology. Dissertations

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The proliferation of portable communication devices combined with the relentless demand for higher data rates has spurred the development of wireless communication standards which can support wide signal bandwidths. Benefits of the complementary metal oxide semiconductor (CMOS) process such as high device speeds and low manufacturing cost have rendered it the technology of choice for implementing wideband wireless transceiver integrated circuits (ICs). This dissertation addresses the key challenges encountered in the design of wideband wireless transceiver ICs. It is divided into two parts. Part I describes the design of crucial circuit blocks such as a highly selective wideband radio frequency (RF) front-end and an on-chip test module which are typically found in wireless receivers. The design of high-speed, capacitive DACs for wireless transmitters is included in Part II. The first work in Part I is the design and implementation of a wideband RF frontend in 65-nm CMOS. To achieve blocker rejection comparable to surface-acousticwave (SAW) filters, the highly selective and tunable RF receiver utilizes impedance transformation filtering along with a two-stage architecture. It is well known that the low-noise amplifier (LNA) which forms the first front-end stage largely decides the receiver performance in terms of noise figure (NF) and linearity (IIP3/P1dB). The proposed LNA uses double cross-coupling technique to reduce NF while complementary derivative superposition (DS) and resistive feedback are employed to achieve high linearity. The resistive feedback also enhances input matching. In measurements, the front-end achieves performance comparable to SAW filters with blocker rejection greater than 38 dB, NF 3.2-5.2 dB, out-of-band IIP3 > +17 dBm and blocker P1dB > +5 dBm over a frequency range of 0.5-3 GHz. The second work in Part I is the design of an RF amplitude detector for on-chip test. As the complexity of RF ICs continues to grow, the task of testing and debugging Preface This Ph.D thesis presents my research work during the period January 2011 to January 2016 at the Division of Integrated Circuits and Systems (EKS), Department of Electrical Engineering (ISY), Linköping University, Sweden. I have spent 4 years (80% of the total 5 years) on research and course work of at least 90 Europen Credit Transfer System (ECTS). The 20% left which is 1 year is used for full-time teaching duties. The dissertation is mainly based on the following peer-reviewed journal articles and conference publications:

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