A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS

Kapusta, Ron; Shen, Junhua; Decker, S.; Li, Hongxing; Ibaragi, Eitake; Zhu, Hai‐Liang

doi:10.1109/jssc.2013.2274113

Cited by 116 publications

(52 citation statements)

References 23 publications

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“…Here primary plate of bridge capacitor is joined to secondary DAC, such that the linearity error occurred due to parasitic can be minimized. To enable the ADC for correcting under approximation and over approximation decision errors , it is required that the decision levels are shifted to middle of redundancy stage [6], [7].For shifting the level, an additional capacitor is used besides the main capacitance array [5].A new approach is introduced in which decision bit and lower weighted bit are switched simultaneously [8], [9].Once the decision is happened, lower order bit is turn downed to its original state. The secondary bit has a weight equal to the redundancy of decision bit.…”

Section: Proposed Architectural Implementation Of Sar-adcmentioning

confidence: 99%

A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices

Dastagiri¹,

Kishore²

2018

IJET

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This brief presents a 10kS/s 14 bit 12.5 ENOB Successive Approximation Register Analog-to-Digital Converter for Cardiac Implantable Medical. For achieving power efficient operation, SAR ADC employ SAR control, a new power and noise efficient comparator topology, non-binary weighted capacitive DAC. The linearity of implemented SAR ADC is enhanced with the uniform geometry of non-binary weighted capacitive DAC.The proposed SAR ADC is implemented using 65nm CMOS technology. The latched comparator consumes a power of 2.4uW and it provides an ENOB of 12.6 at a supply voltage of 1V.The INL is between -2.7/+1.6 LSB and DNL is between -0.6/+1.4LSB. The FOM of ADC is 40fJ/conv.Step which is comparable with existing ADC topologies.

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Section: Proposed Architectural Implementation Of Sar-adcmentioning

confidence: 99%

A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices

Dastagiri¹,

Kishore²

2018

IJET

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“…If this single stage is followed by another stage, the noise of the following stage will contribute to the total noise of the previous stage. Equation (6) could stand for the total output noise for each cell. So for the multi-stage charge pump, the total input referred noise can be derived as…”

Section: Noise Analysismentioning

confidence: 99%

“…The successive approximation register analog-to-digital converters (SAR ADCs) can provide highly power efficiency solution at moderate resolutions, but achieving a SAR ADC with effective number of bits (ENOB) beyond 12 bits shows enormous challenges due to the influence from comparator noise and capacitor mis-matching [4][5][6]. The SAR-assisted pipeline ADC is an energy-efficient architecture for high resolution [7].…”

Section: Introductionmentioning

confidence: 99%

A pipelined SAR ADC with gain-stage based on capacitive charge pump

Chen

Alvandpour

2016

Analog Integr Circ Sig Process

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This paper presents a 14-bit, tunable bandwidth two-stage pipelined successive approximation analog to digital converter which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high DC gain requirement of operational transconductance amplifier in the gain-stage, the multi-stage capacitive charge pump (CCP) was utilized to achieve the gain-stage instead of using the switch capacitor integrator. The detailed design considerations are given in this work. Thereafter, the 14-bit ADC was designed and fabricated in a low-cost 0.35-lm CMOS process. The prototype ADC achieves a peak SNDR of 75.6 dB at a sampling rate of 20 kS/s and 76.1 dB at 200 kS/s while consuming 7.68 and 96 lW, respectively. The corresponding FoM are 166.7 and 166.3 dB. Since the bandwidth of CCP is tunable, the ADC maintains a SNDR [75 dB upto 260 kHz. The core area occupied by the ADC is 0.589 mm 2 .

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“…This in turn will cause the DAC output to ring [72]. The bondwire inductance depends on the dimensions of the gold wire used in bonding.…”

Section: Limitations For Dac Settlingmentioning

confidence: 99%

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

Harikumar¹

2016

Linköping Studies in Science and Technology. Dissertations

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Analog-to-digital converters (ADCs) are crucial blocks which form the interface between the physical world and the digital domain. ADCs are indispensable in numerous applications such as wireless sensor networks (WSNs), wireless/wireline communication receivers and data acquisition systems. To achieve long-term, autonomous operation for WSNs, the nodes are powered by harvesting energy from ambient sources such as solar energy, vibrational energy etc. Since the signal frequencies in these distributed WSNs are often low, ultra-low-power ADCs with low sampling rates are required. The advent of new wireless standards with ever-increasing data rates and bandwidth necessitates ADCs capable of meeting the demands. Wireless standards such as GSM, GPRS, LTE and WLAN require ADCs with several tens of MS/s speed and moderate resolution (8-10 bits). Since these ADCs are incorporated into battery-powered portable devices such as cellphones and tablets, low power consumption for the ADCs is essential.The first contribution is an ultra-low-power 8-bit, 1 kS/s successive approximation register (SAR) ADC that has been designed and fabricated in a 65-nm CMOS process. The target application for the ADC is an autonomously-powered soil-moisture sensor node. At V DD = 0.4 V, the ADC consumes 717 pW and achieves an FoM = 3.19 fJ/conv-step while meeting the targeted dynamic and static performance. The 8-bit ADC features a leakage-suppressed S/H circuit with boosted control voltage which achieves > 9-bit linearity. A binary-weighted capacitive array digital-to-analog converter (DAC) is employed with a very low, custom-designed unit capacitor of 1.9 fF. Consequently the area of the ADC and power consumption are reduced. The ADC achieves an ENOB of 7.81 bits at near-Nyquist input frequency. The core area occupied by the ADC is only 0.0126 mm 2 .The second contribution is a 1.2 V, 10 bit, 50 MS/s SAR ADC designed and implemented in 65 nm CMOS aimed at communication applications. For medium-tohigh sampling rates, the DAC reference settling poses a speed bottleneck in chargeredistribution SAR ADCs due to the ringing associated with the parasitic inductances. Although SAR ADCs have been the subject of intense research in recent years, scant attention has been laid on the design of high-performance on-chip reference voltage buffers. The estimation of important design parameters of the buffer as well iv critical specifications such as power-supply sensitivity, output noise, offset, settling time and stability have been elaborated upon in this dissertation. The implemented buffer consists of a two-stage operational transconductance amplifier (OTA) combined with replica source-follower (SF) stages. The 10-bit SAR ADC utilizes split-array capacitive DACs to reduce area and power consumption. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the ...

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A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS

Cited by 116 publications

References 23 publications

A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices

A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices

A pipelined SAR ADC with gain-stage based on capacitive charge pump

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

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