A 147 μW, 0.8 V and 7.5 (mV/V) LIR regulator for UHF RFID application

Salehi, Mohammad Reza; Dastanian, Rezvan; Abiri, Ebrahim; Nejadhasan, Sajad

doi:10.1016/j.aeue.2014.08.004

Cited by 13 publications

(3 citation statements)

References 10 publications

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“…The limiter block prevents voltage increments and possible damage to the circuit when the transmitter and receiver are near to each other. In the next step, the voltage regulator also eliminates the ripples of the rectifier output signal and the voltage obtained with DC to DC converter is changed to different voltage level to supply other circuit blocks [17].…”

Section: Proposed DC Voltage Limitermentioning

confidence: 99%

A 2V, 32.13nA, fully MOSFET Voltage Limiter for Low Power Applications

Rayat¹,

Dastanian²

2022

RADIOENGINEERING

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This paper presents a fully MOSFET DC voltage limiter with low current consumption. In the proposed voltage reference structure to reduce power consumption, transistors are biased in the sub-threshold region. To generate complementary to absolute temperature (CTAT) voltage in the voltage reference circuit, only a PMOS transistor is used, in which its drain, gate, and source terminals are connected together and acts as a diode that reduces the layout area occupation. To further reduce power consumption, a part of the rectifier output voltage is compared with the reference voltage by the sampling circuit. Also, four stage inverters are used as buffers to provide the I-V limiting characteristic closer to the ideal situation. The use of series pass-gate transistors in the first inverter also reduces power consumption as much as possible.The results of post-layout simulation based on 0.18μm CMOS technology depict that the suggested voltage reference circuit has a reference voltage equivalent to 0.579 V with a TC of 37.2 ppm/°C in the temperature range of -50°C to 50°C. LR and PSRR attained 0.008%/V and 45 dB, respectively. The output voltage and current consumption of the limiter circuit are 2 V and 32.13 nA, respectively. The total layout area of the proposed limiter is 3249 μm 2 .

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Section: Proposed DC Voltage Limitermentioning

confidence: 99%

A 2V, 32.13nA, fully MOSFET Voltage Limiter for Low Power Applications

Rayat¹,

Dastanian²

2022

RADIOENGINEERING

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“…Finally, it can be concluded that the diodebased voltage references suffer from large process variations and low‐temperature stability, whereas BJT‐based voltage references require higher power supply and larger chip area than MOS‐based voltage references 44,45 . Also, some of the reported voltage references with high‐order curvature compensation techniques use operational amplifiers to compensate the temperature coefficient, which further increase the complexity and area of the circuits.…”

Section: Introductionmentioning

confidence: 99%

Low temperature coefficient and low line sensitivity subthreshold curvature‐compensated voltage reference

Thakur

Pandey

Kumar

2020

Circuit Theory & Apps

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Summary A high‐order curvature‐compensated subthreshold voltage reference is proposed in this paper. The proposed curvature‐compensated voltage reference consists of two supply‐independent first‐order voltage references and a curvature compensation circuit. The supply‐independent first‐order voltage reference uses a negative feedback loop which improves the line sensitivity and eliminates the demand of operational amplifier, whereas the curvature compensation circuit provides high‐order temperature‐compensated output reference voltage. The proposed curvature‐compensated voltage reference provides an output reference voltage of 118.54 mV with a temperature coefficient of 21.5 ppm/°C over a wide temperature range of −60°C to 120°C. The power supply rejection ratio and line sensitivity are observed as −68.64 dB (for the frequency range of 1 Hz to 100 Hz) and 0.035%/V (for the supply voltage varies from 0.85 V to 2.5 V), respectively. The values of output noise at the frequencies of 1 kHz and 10 kHz without using any capacitive filter are obtained as 179.13 nV/ √ Hz and 123.87 nV/ √ Hz, respectively.

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“…The main core of the PTAT generator includes two NMOS transistors, which are connected to each other, and the output of the PTAT generator is the difference of the gate-source voltages of these two transistors [13,14].…”

Section: Ptat and Ctat Voltage Generatorsmentioning

confidence: 99%