A 14-nm Ultra-Low Jitter Fractional-<i>N</i> PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO

Wu, Wanghua; Yao, Chunhua; Guo, Chengkai; Chiang, Pei-Yuan; Chen, Lei; Lau, Pak-Kim; Bai, Zhanjun; Son, Sang Won; Cho, Thomas Byunghak

doi:10.1109/jssc.2021.3111134

Cited by 49 publications

(12 citation statements)

References 33 publications

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“…Under a 1-V supply (the nominal supply of transistors used in the implemented TAU), the INL is 1.7 LSB, corresponding to 0.17% of the full range. This is better than the DTC INL of 0.4% in [42] but worse than that of 0.09% in [41] (both from simulations). The TAU's INL is mainly degraded by the offsets between the coarse-tuning segments, reflecting the contribution from the charge injection of SR units.…”

Section: B Simulated Inlmentioning

confidence: 60%

A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit

Gao

Fritz

et al. 2023

IEEE J. Solid-State Circuits

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This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs-the period of a digitally controlled oscillator (DCO) and the instantaneous time offset between the DCO and reference clock edges-and then extracts the DCO phase error by calculating their weighted sum. The prototype, implemented in 40-nm CMOS, achieves 182-fs rms jitter with 3.5-mW power consumption. In a near-integer channel, it shows the worst fractional spur below −59 dBc. Under considerable supply or temperature variations, the worst spur still remains below −51.7 dBc without any background calibration tracking. Index Terms-Digital-to-time converter (DTC), fractional spur, phase-locked loop (PLL), process voltage and temperature (PVT), time-mode arithmetic unit (TAU). I. INTRODUCTIONT HE sub-sampling technique [1], [2], [3], [4], [5] and, more specifically, the narrow-range phase-detection concept [6], [7] have contributed to a significant improvement of phase noise (PN) in phase-locked loops (PLLs). Such techniques ensure that the phase detector (PD) can expect a

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Section: B Simulated Inlmentioning

confidence: 60%

A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit

Gao

Fritz

et al. 2023

IEEE J. Solid-State Circuits

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“…A well-defined CM return path is necessary for achieving low flicker PN, especially in mm-wave oscillators [54]. Surprisingly, the CM return path in a QOSC is altogether different from that in the conventional single-core [55] or dual-core oscillators (see [77,Fig. 13]).…”

Section: B Qdco's CM Return Path and Decoupling Schemementioning

confidence: 99%

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness

Chen

Siriburanon

et al. 2023

IEEE J. Solid-State Circuits

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In this article, we present a low phase noise (PN) mm-wave quadrature digitally controlled oscillator (DCO) exploiting transformers for class-F operation and harmonic extraction. A third transformer coil is added for the inter-core coupling with the source terminals of the switching transistors. We identify that the inter-core coupling in quadrature oscillators causes an asymmetric flicker noise current, thus degrading flicker PN. As a remedy, we propose a deliberate drain-to-gate phase shift of the switching transistors by means of capacitive loading to fix this asymmetry. The ±90 • I/Q mode ambiguity is also resolved by introducing another phase shift in the source-coupling; it is explained by a simplified analysis with phasor diagrams. Fabricated in the TSMC 28-nm LP CMOS, the prototype achieves PN of −112 dBc/Hz and figure-of-merit (FoM) of −185 dB at 1-MHz offset of 25.7 GHz. The measured flicker PN corner is 140-250 kHz and image rejection ratio (IRR) >47 dB over the whole 18% tuning range (TR). To the best of the authors' knowledge, it is the best reported PN and IRR for a mm-wave quadrature oscillator.

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“…5 The PD-gain (i.e., slope or TD-gain) from the reference's sinusoidal waveform is roughly N× lower than from the oscillator's, thus limiting the jitter performance. A remedy proposed in [9], [11] is to condition the reference's or divider's waveform by a sharp RC filter before sampling.…”

Section: ) Adc-based Tdcmentioning

confidence: 99%

Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial

Siriburanon

Staszewski

2022

IEEE Trans. Circuits Syst. II

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In this tutorial brief, we introduce a unified wideband phase-noise theory framework of frequency synthesis based on a multirate timestamp modeling with "two z-variables". We apply it to model and analyze two types of ultra-low jitter (i.e., sub-50 fs) phase-locking techniques: 1) high-bandwidth PLLs with high phase-detector gain (with emphasis on all-digital PLLs), and 2) injection locking (IL) or recently proposed charge-sharing locking (CSL), serving as a unified guide on achieving the sub-50 fs jitter. All analytical results are numerically verified through time-domain behavioral simulations, demonstrating that the theoretically maximum bandwidths are around 30% and 44% of the reference frequency in PLLs and IL, respectively.

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A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO

Cited by 49 publications

References 33 publications

A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit

A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness

Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial

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