A 14-bit Digitally Self-Calibrated Pipelined ADC With Adaptive Bias Optimization for Arbitrary Speeds Up to 40 MS/s

Iizuka, Kunihiko; Matsui, Hirofumi; Ueda, Mitsuru; Daito, Mutsuo

doi:10.1109/jssc.2006.870788

Cited by 43 publications

(13 citation statements)

References 16 publications

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“…However, these existing approaches suffer from various penalties. For example, the earliest evolving foreground calibration discussed in [22], [23] requires switching the precise analog circuitry in and out of the pipeline to connect it to a special set of input signals, which adds overheads to the analog front-end by introducing additional capacitances and/or shortening effective conversion time. The dithering-based digital calibration presented in [15], [24] suffers from slow convergence speed and relatively low accuracy due to limited dithering magnitude and strong interference from the input signal, which impede its spread in applications that support intermittent operation.…”

Section: Digital Calibrationmentioning

confidence: 99%

“…By adopting an 1-bit redundancy pipeline stage, the actual bit-weight measurement can be performed by applying a single zero input instead of the special set of input signals in traditional implementations [22], [23]. Meanwhile, a complete auxiliary reconfiguration scheme is designed to keep the analog-signal path completely intact and a compact digital algorithm is employed to save hardware resources and power consumption.…”

Section: Digital Calibrationmentioning

confidence: 99%

“…A traditional method to measure the bit weight is to quantize the residual output voltages, while fixing the input at a specific voltage to make sure that the digitalized value is corresponding to the bit weight of the measuring capacitor [23]. For the conventional 0.5-bit redundancy pipeline stage, additional driving circuitry is needed to provide the specific input voltages for the measurements of difference capacitors.…”

Section: B Calibration Configuration In Pipeline Stagesmentioning

confidence: 99%

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A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

Zheng

Wang

et al. 2016

IEEE Trans. Circuits Syst. I

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Abstract-This paper presents a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity, operating speed, and power efficiency. The implemented ADC employs an improved SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a wide input frequency range. It also explores a dedicated foreground calibration to correct the capacitor mismatches and the gain error of residue amplifier, where a novel configuration scheme with little cost for analog front-end is developed. Moreover, a partial non-overlapping clock scheme associated with a highspeed reference buffer and fast comparators is proposed to maximize the residue settling time. The implemented ADC is measured under different input frequencies with a sampling rate of 250 MS/s and it consumes 300 mW from a 1.8 V supply. For 30 MHz input, the measured SFDR and SNDR of the ADC is 94.7 dB and 68.5 dB, which can remain over 84.3 dB and 65.4 dB for up to 400 MHz. The measured DNL and INL after calibration are optimized to 0.15 LSB and 1.00 LSB, respectively, while the Walden FOM at Nyquist frequency is 0.57 pJ/step.

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Section: Digital Calibrationmentioning

confidence: 99%

Section: Digital Calibrationmentioning

confidence: 99%

Section: B Calibration Configuration In Pipeline Stagesmentioning

confidence: 99%

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A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

Zheng

Wang

et al. 2016

IEEE Trans. Circuits Syst. I

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“…The Pipeline or Subrange ADCs (Ahmed & Johns,2005) (Iizuka et al,2006) achieve conversion speeds comparable to that of the Flash ADCs with significantly lower power consumption and die area. The principle of their operation is described by Fig.…”

Section: Pipeline Adcsmentioning

confidence: 99%

Asynchronous Analogue-to-Digital Conversion Techniques

Petrellis¹,

Birbas²,

Kikidis³

et al. 2010

Factory Automation

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“…A digital calibration of the capacitor mismatch, the comparator offsets and the charge injection offsets in a pipelined ADC is performed in (Karanicolas et al, 1993) for the improvement of DNL errors. The biasing of the operational amplifiers used in a pipelined ADC according to the power supply, the temperature and the sampling speed is determined by calibration in (Iizuka et al, 2006). The offset of the residue amplifiers is calibrated in the background in (Ploeg et al, 2005) (Van De Vel, 2009).…”

Section: Introductionmentioning

confidence: 99%