A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration

Daito, Mutsuo; Matsui, Hirofumi; Ueda, Mitsuru; Iizuka, Kunihiko

doi:10.1109/jssc.2006.882886

Cited by 36 publications

(4 citation statements)

References 13 publications

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“…While all gain errors in the signal path can be simultaneously calibrated with the proposed calibration method, to avoid introducing large nonlinear inter-stage errors [9,10] , the circuit implementation should ensure that all components are linear enough to achieve high SFDR. Single-stage folded cascade op-amp is used in SHA and other pipelined stages to obtain excellent bandwidth and output swing for low voltage application.…”

Section: Circuit Implementationmentioning

confidence: 99%

A 12-bit 100 MS/s pipelined ADC with digital background calibration

Zhou¹,

Luo²,

Ye³

et al. 2009

J. Semicond.

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This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter (ADC) with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter (MDAC) while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18 μm CMOS process, occupies an active area of 2.3 × 1.6 mm2, and consumes 205 mW at 1.8 V.

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Section: Circuit Implementationmentioning

confidence: 99%

A 12-bit 100 MS/s pipelined ADC with digital background calibration

Zhou¹,

Luo²,

Ye³

et al. 2009

J. Semicond.

View full text Add to dashboard Cite

show abstract

“…Due to the relaxed gain requirement, the conversion opamp can be realized with the one-stage cascode type without gainboosting [2], [6]. Compared with the multistage opamp, approximately half of the power consumption can be saved [7] and no Miller capacitors are needed.…”

Section: Continuous Reference Refreshing and Calibrationmentioning

confidence: 99%

A 10-bit pipeline ADC using 40-dB opamps and calibrated customized references

Chen

Yuan

2007

2007 7th International Conference on ASIC

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A 10-bit pipeline A/D converter using low gain ( 40 dB) operational amplifiers (opamps) is presented. Without interfering the normal analog-to-digital conversion, a continuous reference refreshing technique is exploited. This technique effectively reduces the gain requirement of opamp while the conversion speed is not compromised, allowing the use of simple cascode CMOS inverters. The compensation of finite gain of the opamp is made by using customized reference voltages that is calibrated periodically. The technique has been confirmed by intensive simulations. As a result of the relaxed opamp gain requirement, significant reduction in power consumption can be achieved.

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“…Calibration algorithms have been proposed to compensate harmonic distortions introduced by finite opamp gain in Refs. [6][7][8][9][10][11][12] and become a mainstream.…”

Section: Introductionmentioning

confidence: 99%

A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR

Zhao¹,

Wei²,

Yang³

et al. 2014

J. Semicond.

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This paper demonstrates a 14-bit 100 MS/s CMOS pipelined analog-to-digital converter (ADC). The nonlinearity model for bootstrapped switches is established to optimize the design parameters of bootstrapped switches, and the calculations based on this model agree well with the measurement results. In order to achieve high linearity, a gradient-mismatch cancelling technique is proposed, which eliminates the first order gradient error of sampling capacitors by combining arrangement of reference control signals and capacitor layout. Fabricated in a 0.18-m CMOS technology, this ADC occupies 10.16-mm 2 area. With statistics-based background calibration of finite opamp gain in the first stage, the ADC achieves 83.5-dB spurious free dynamic range and 63.7-dB signalto-noise-and distortion ratio respectively, and consumes 393 mW power with a supply voltage of 2 V.

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A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration

Cited by 36 publications

References 13 publications

A 12-bit 100 MS/s pipelined ADC with digital background calibration

A 12-bit 100 MS/s pipelined ADC with digital background calibration

A 10-bit pipeline ADC using 40-dB opamps and calibrated customized references

A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR

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