A 14.6&lt;sup&gt;th&lt;/sup&gt;-order 3.456GHz transmit baseband filter in 110nm CMOS for millimeter-wave communication systems

Michiko, Tokumaru; Ikoma, Heiji; Yamada, Yuji; Okamoto, K.; Yamamoto, Akira; Shirakawa, Yoshinori

doi:10.1109/cicc.2009.5280872

Cited by 9 publications

(13 citation statements)

References 3 publications

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“…The M:1 MUX could be implemented in one step itself or be pipelined into individual multiplexing stages progressively increasing in frequency. This traditional scheme has been used in [34] and [46] to serialize 8 channels to frequencies of 2.5 GHz and 3.456 GHz respectively using static CMOS logic styles. However, achieving higher frequencies using this scheme is challenging due to the shrinking timing window for the multiplexing.…”

Section: Choice Of Multiplexing Strategymentioning

confidence: 99%

“…On the other hand, DACs for wireless applications that connect to an upconversion mixer require relatively a lower swing e.g. 0.3 V in [8], 0.6 V in [46]. In the case of a ∆Σ DAC, the number of bits in the DAC is decided by the SQNR/SNDR required while the output swing is decided by the application.…”

Section: Dac Current Cell Designmentioning

confidence: 99%

“…Two sine generators are required to perform a two-tone testing [16]. In addition, PRBS generators may be required to test the spectral mask of a given standard [46]. A drawback with sine generators is that they also contain large feedback paths similar to integrators.…”

Section: Dac Testing Challengesmentioning

confidence: 99%

“…DACs that form a part of the transmitter baseband are hence required to have a wide bandwidth >880 MHz (in both, I & Q paths to enable the 1.76 GHz channel BW) and a resolution >6-8 bits to support the different modulation schemes of these standards [7,46,[70][71][72]. Most of the DACs reported in literature for 60-GHz radio have so far used a conventional approach with a 2× digital interpolation of the baseband, followed by a Nyquist current-steering DAC and a fourth or fifth order passive LC-analog anti-aliasing filter, which then connects to an up-conversion 76 A 11-GS/s 1.1-GHz BW TI-∆Σ DAC for 60-GHz Radio in 65-nm CMOS mixer [46,70].…”

Section: Introductionmentioning

confidence: 99%

“…Most of the DACs reported in literature for 60-GHz radio have so far used a conventional approach with a 2× digital interpolation of the baseband, followed by a Nyquist current-steering DAC and a fourth or fifth order passive LC-analog anti-aliasing filter, which then connects to an up-conversion 76 A 11-GS/s 1.1-GHz BW TI-∆Σ DAC for 60-GHz Radio in 65-nm CMOS mixer [46,70]. This approach is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

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Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Bhide

2015

Linköping Studies in Science and Technology. Dissertations

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Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for high-data-rate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconfiguration for multiple radio standards. ∆Σ DACs can fit very well into this trend of digital architectures as they contain a large digital signal processing component and offer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction filter order is reduced.Achieving a large bandwidth from ∆Σ DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ∆Σ DAC architectures, even in nanometer CMOS processes. Time-interleaved ∆Σ (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs.The first work is an 8-GS/s interleaved ∆Σ DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ∆Σ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, −57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to iv be limited by the testing setup for sending high-speed digital data into the prototype.The performance of a two-channel interleaved ∆Σ DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this effect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 − z −1 ) n . It is shown that a low-order FIR filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. The...

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Section: Choice Of Multiplexing Strategymentioning

confidence: 99%

Section: Dac Current Cell Designmentioning

confidence: 99%

Section: Dac Testing Challengesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Bhide

2015

Linköping Studies in Science and Technology. Dissertations

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Case Study 2: DSIP Architecture Instances for FIR Filtering

Fasthuber¹,

Catthoor²,

Raghavan³

et al. 2013

Energy-Efficient Communication Processors

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Design and analysis of high-speed split-segmented switched-capacitor DACs

Duong

Bhide

Alvandpour

2017

Analog Integr Circ Sig Process

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In order to achieve high speed and high resolution for switched-capacitor (SC) digital-to-analog converters (DACs), an architecture of split-segmented SC DAC is proposed. The detailed design considerations of kT/C noise, capacitor mismatch, settling time and simultaneous switching noise (SSN) are mathematically analyzed and modelled. The design area W-Cu is defined based on that analysis. It is used not only to identify the maximum speed and resolution but also to find the design point (W, Cu) for certain speed and resolution of SC DAC topology. The segmentation effects are also considered. An implementation example of this type of DACs is a 12-bit 6-6 split-segmented SC DAC designed in 65 nm CMOS. The linear open-loop output driver utilizing derivation superposition (DS) technique for nonlinear cancellation is used to drive off-chip load for the SC array without compromising its performance. The measured results show that the SC DAC achieves a 44 dB spurious free dynamic range (SFDR) within a 1 GHz bandwidth of input signal at 5 GS/s while consuming 50 mW from 1 V digital and 1.2 V analog supplies. The overall performance that was achieved from measurement is poorer than expected due to lower power supply rejection ratio (PSRR) in fabricated chip. This DAC can be used in transmitter baseband for wideband wireless communications.Index Terms-high-speed DACs, SC DACs, 12-bit splitsegmented DACs, linear output driver, wideband wireless communications. Clk-Clk+ Out+ Decoder

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A 14.6<sup>th</sup>-order 3.456GHz transmit baseband filter in 110nm CMOS for millimeter-wave communication systems

Cited by 9 publications

References 3 publications

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Case Study 2: DSIP Architecture Instances for FIR Filtering

Design and analysis of high-speed split-segmented switched-capacitor DACs

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